Table 1 Summary of state-of-the-art III-V TFET demonstrations

From: InAs/Si Hetero-Junction Nanotube Tunnel Transistors

Affiliation

Ref.

Year

Technology

Material System

Ion(A) per nanowire

Ion(µA /µm)

SS (mV/dec)

Penn State

[26]

2010

Non planar single gate

In0.53Ga0.47As

NA

4×10−1

100–216

Intel

[27]

2011

Planar

InGaAs

NA

~ 7

60

UC Berkeley

[11]

2011

Planar

InAs

NA

0.5

190

Univ. of Notre Dame

[28]

2011

Vertical InGaAs/ InP

InGaAs

NA

20

130

IBM

[29]

2011

GAA NW

InAs/Si

10−7

0.4

220

UT Austin

[30]

2011

Vertical single gate

In0.7Ga0.3As

NA

40

84–380

IBM

[24]

2012

GAA NW

InAs/Si

Not reported

2.4

150

Hokkaido Univ

[31]

2012

Vertical hetero NW

InAs/Si

Not reported

~ 0.005

21 / 114

Univ. of Notre Dame

[32]

2012

Planar single gate

GaSb-InAs

NA

180

200–400

Univ. of Notre Dame

[33]

2012

Planar single gate

InP-InGaAs

NA

20

93–310

Penn State

[34]

2012

Vertical single gate

GaAsSb-InGaAs

NA

135

230–350

Univ. of Notre Dame

[35]

2012

Planar single gate

AlGaSb-InAs

NA

78

125–470

Hokkaido Univ

[12]

2013

Vertical hetero NW

InAs/Si

Not reported

1

21

MIT

[36]

2013

Vertical single gate

InGa0.53As0.47-GaAs0.5Sb0.5

NA

0.5

140