Table 1 Estimation and comparison between CMOS, benchmarked SWD and our proposed SWD. The data for CMOS and SWD is based on the benchmarking proposed in [2,3].

From: Non-volatile Clocked Spin Wave Interconnect for Beyond-CMOS Nanomagnet Pipelines

  

CMOS HP 2, 3

CMOS LP 2, 3

SWD 2, 3

SWD (this work)

Inverter with fanout 1

area

0.036 μ2

0.036 μ2

0.0162 μ2

0.0128 μ2

 

energy

31.2 aJ

5.27 aJ

4.51 aJ

26 aJ

 

delay

0.78 ps

97.6 ps

0.45 ns

2 ns

State element

area

0.648 μ2

0.648 μ2

0.0162 μ2

0.0128 μ2

 

energy

0.45 fJ

76.8 aJ

4.51 aJ

26 aJ

 

delay

9.73 ps

1.2 ns

0.45 ns

2 ns

first stage optional input*

energy

—

—

—

7 fJ

  1. *STT used in C-S converter for storing either bit 1 or 0.