Figure 1
From: Stacked 3D RRAM Array with Graphene/CNT as Edge Electrodes
The typical schematic of 3D RRAM architecture.
The sneak path currents exist in each vertical plane which dominates the maximum number of cells in the array. Therefore, the selector is a critical element to cut off the sneak path and achieve high density integration. The feature size scaling down of 3D RRAM can be divided into two parts: 1) the vertical direction decided by the thickness of metal plane; 2) the horizontal direction determined by the thickness of metal pillar, resistive switching layer and selector layer.
