Figure 4 | Scientific Reports

Figure 4

From: Thickness scaling of atomic-layer-deposited HfO2 films and their application to wafer-scale graphene tunnelling transistors

Figure 4

(a) Optical image of the MOG-FET arrays fabricated on a 6″ Si wafer and a schematic illustration showing the structure of the MOG-FET device. (b) Optical microscope image of a fabricated MOG-FET unit device. (c) Cross sectional TEM image showing the HfO2 gate dielectric layer with a thickness of ~5 nm (including the seed layer converted to a HfO2 layer) on monolayered graphene. (d) Statistical distribution of the sheet resistance of a monolayered graphene before and after the ALD of HfO2 with and without an e-beam-evaporated Hf seed layer. Representative electrical characteristics measured from the fabricated MOG-FET devices: (e) gate dielectric leakage current, (f) gate capacitance as a function of the frequency, and (g) transfer curve (ID-VG).

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