Figure 1: PMC operation principle and device structure.
From: Integrated photonics with programmable non-volatile memory
(a) Cross-sectional schematic of PMC showing the floating gate (FG) stack with separated n++ source (S) and p++ drain (D) configuration. The FG is doped n+ and p+ at the drain and source end, respectively. The control gate (CG) overlaps the FG partially at the source side. The FG stack at the drain is characteristic of a programmable MOS optical waveguide (WG). Black arrows denote the carrier movement during program and erase operation in a continuous flow. (b) Tilt schematic view of the MRR with the PMC and a ridge optical bus waveguide. (c) Cross-sectional SEM of the fabricated device. The radius of MRR is 10 μm, and both the MRR waveguide and bus waveguide widths were 500 nm. The slab thicknesses is 100 nm. The floating gate and control gate are 100 nm thick, either. (d) High resolution TEM image of the source region whereby the CG overlaps the FG, and (e) the drain region.
