Figure 2
From: Anomalous enhancement of the sheet carrier density beyond the classic limit on a SrTiO3 surface
FET with HfO2 (20 nm)/Parylene-C (6 nm) solid-state bilayer gate insulator studied in this work.
(a) Schematic cross-section image of our three-terminal FET device. (b) Photograph of a 10 mm × 10 mm (100) SrTiO3 substrate with the FET devices fabricated on it. Scanning electron microscopy images of (c) a three-terminal FET device and (d) multi-terminal one. G, S and D stand for gate, source and drain electrodes, respectively. V1–V6 are potential probes.
