Figure 4 | Scientific Reports

Figure 4

From: Approaching Defect-free Amorphous Silicon Nitride by Plasma-assisted Atomic Beam Deposition for High Performance Gate Dielectric

Figure 4

Gate current densities modeling and EOT analysis: (a) Model the gate current densities for 2.1 nm of PA-ABD a-Si3N4 on the p-type Si (100) substrate with dots for experimental data and with red curve for the model of direct tunneling. The top inset is the energy band diagram of the MNS capacitor with a p-type substrate for a negative gate bias and the bottom inset is cross sectional HR TEM image. (b) Plot of leakage current density at 1V of gate voltage versus EOT for SiO241, HfO242,43 and PA-ABD a-Si3N4 for comparison and PA-ABD a-Si3N4 shows a significant leakage current reduction. The criteria of low power limit and gate limit of leakage current densities are taken from previous reports1,44.

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