Figure 2 | Scientific Reports

Figure 2

From: A realistic fabrication and design concept for quantum gates based on single emitters integrated in plasmonic-dielectric waveguide structures

Figure 2

Simplified overview of the different steps during processing of the photonic-plasmonic on-chip structures.

(b–e) Cut along the dashed line in (a). (b) Ni mask (grey) for the dielectric waveguides in Si3N4 (blue), (c) ZEP resist (red)/Si3N4 mask for the plasmonic components after the second etching step, (d) gold evaporation (yellow layer comprises Cu, Au and Ni layers), (e) lift-off of gold on ZEP resist, (f) final etching step (and removal of remaining protective Ni on gold and dielectric structures).

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