Figure 6
From: On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS
(a) Simulated input reflection coefficient (S11) of the designed on-chip SPP T-line with converter for different Cy with d = 12.4 μm, a = 2.4 μm, w = 5 μm and (b) simulated transmission coefficient (S21) of the designed on-chip SPP T-line with converter for different Cy.
