Figure 7
From: On-chip sub-terahertz surface plasmon polariton transmission lines with mode converter in CMOS
(a) Simulated input reflection coefficient (S11) of the designed on-chip SPP T-line with converter for different k with optimized Cy for each cases and (b) simulated transmission coefficient (S21) of the designed on-chip SPP T-line with converter for different k with comparison to conventional on-chip transmission line (T-line).
