Figure 4: Electrical characteristics.

(a) An optical image of the CMOS chip with vertically integrated memristive crossbars: the region highlighted in the red box has the 3D CMOL crossbar structures, (b) A high-resolution optical image of a section of the integrated 3D crossbars. (c) A typical I-V plot measured on a test structure to test the contact resistance between the memristive layer and the underlying CMOS. Inset shows a map of the current measured at all the 24 × 36 array of ‘red pins’ showing contact between the integrated devices and the CMOS cells. Current is measured at 0.2 V for each measurement. (d) An I-V plot showing typical DC switching characteristics of the integrated memristive devices: the device is initially turned on and is gradually reset demonstrating analog switching behavior, (e) pulsed switching characteristic of a device in layer 1 showing gradual reset and set operation: the device is tuned to each desired state using a tuning algorithm (discussed in the supporting info.). The arrow indicates the direction of programming in each case, (f) pulsed switching characteristic of a device in layer 2 showing gradual reset and set operation: the device is tuned to each desired state using the tuning algorithm.