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Showing 1–5 of 5 results

Advanced filters: Author: Mon-Shu Ho Clear advanced filters

A mixed-precision memristor and SRAM compute-in-memory AI processor

A mixed-precision heterogeneous memristor combined with a compute-in-memory artificial intelligence (AI) processor allows optimization of the precision, energy efficiency, storage and wakeup-to-response time requirements of AI edge devices, which is demonstrated using existing models and datasets.

Win-San Khwa
Tai-Hao Wen
Meng-Fan Chang
Research05 Mar 2025
Nature

Volume: 639, P: 617-623
A CMOS-integrated spintronic compute-in-memory macro for secure AI edge devices

A non-volatile compute-in-memory macro that is based on spin-transfer torque magnetic random-access memory can offer secure access control, data protection, rapid response times and high energy efficiency for dot-product edge computing.

Yen-Cheng Chiu
Win-San Khwa
Meng-Fan Chang
Research13 Jul 2023
Nature Electronics

Volume: 6, P: 534-543
A four-megabit compute-in-memory macro with eight-bit precision based on CMOS and resistive random-access memory for AI edge devices

Advanced complementary metal–oxide–semiconductor technology and resistive random-access memory can be used to create high-bit-precision compute-in-memory macros for low latency and efficient edge computing.

Je-Min Hung
Cheng-Xin Xue
Meng-Fan Chang
Research20 Dec 2021
Nature Electronics

Volume: 4, P: 921-930
A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

Commercial complementary metal–oxide–semiconductor and resistive random-access memory technologies can be used to create multibit compute-in-memory circuits capable of fast and energy-efficient inference for use in small artificial intelligence edge devices.

Cheng-Xin Xue
Yen-Cheng Chiu
Meng-Fan Chang
Research14 Dec 2020
Nature Electronics

Volume: 4, P: 81-90
CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors

A 1 Mb non-volatile computing-in-memory system, which integrates a resistive memory array with control and readout circuits using an established 65 nm foundry CMOS process, can offer high energy efficiency and low latency for Boolean logic and multiply-and-accumulation operations.

Wei-Hao Chen
Chunmeng Dou
Meng-Fan Chang
Research26 Aug 2019
Nature Electronics

Volume: 2, P: 420-428