Fig. 2: Device characteristics of nonvolatile FeTFT for readout network.
From: Analog reservoir computing via ferroelectric mixed phase boundary transistors
a Schematic illustration and cross-sectional view of the nonvolatile FeTFT with an MFMIS structure. b Cross-sectional TEM images of the fabricated FeTFT. Magnified TEM image of the red dashed square region presents the thickness of each layer: metal (M), ferroelectric (FE), inner metal (IM), interlayer oxide (IL), and IGZO channel. c Top optical images of the FeTFT array. The FeTFT array has an AND-type array configuration, characterized by bit-lines (BLs) and source-lines (SLs) parallel to each other yet perpendicular to word-lines (WLs). The gate (G), source (S), and drain (D) electrodes of each FeTFT within the array are accessible via WL, SL, and BL, respectively. The width (W) and length (L) of a channel are both 20 μm. d Switching current and P-V hysteresis loop through the PUND measurements with 100 kHz triangular pulses. e Hysteretic transfer characteristics (ID-VGS) measured with a bidirectional direct current (DC) sweep of the gate voltage (VGS), ranging from –4.0 V to 4.0 V. A drain-source voltage (VDS) is 0.1 V. The FeTFT exhibits a wide memory window (MW) of approximately 2.2 V at a constant ID of 10 nA. f LTP and LTD characteristics of the FeTFT with the number of applied pulses. The insets show the schematics of applied PGM and ERS pulses. The FeTFT achieves multilevel synaptic weights with a highly linear conductance response. g LTP and LTD characteristics over 20 cycles, with each cycle containing 32 applied pulses. The FeTFT exhibits low cycle-to-cycle variation. h Retention characteristics of eight different conductance states at room temperature.
