Fig. 3: Silicon measurements of a single plastic synapse and its neuron, demonstrating local synaptic plasticity.
From: A neuromorphic processor with on-chip learning for beyond-CMOS device integration
a A presynaptic spike train induces a current (blue) read by the spiking Analog-to-Digital Converter (sADC), while simultaneous stimulation with an Excitatory Post Synaptic Current (EPSC) triggers postsynaptic spiking (green). Shaded regions indicate when the post-trace exceeds the lower threshold, reflecting short-term memory. The Ca2+ trace (orange) accumulates postsynaptic activity, showing plasticity when above its threshold. b STDP measurements assess the impact of pre- and postsynaptic spike timing, \(\Delta t={{{\rm{pre}}}}-{{{\rm{post}}}}\), on the analog weight of the synapse (w). This is the most expressive STDP curve achievable on-chip where all potentiation and depression branches of the learning circuitry are active. c This STDP curve demonstrates modulation of potentiation and depression through analog biasing. In this experiment the effect of depression with positive Δt timings was switched off. d SRDP results show the probability of the synapse maintaining high or low weight based on pre- and postsynaptic firing rates (\({\nu }_{{{{\rm{pre}}}}}\) and νpost). e The plasticity circuit in each synapse uses three analog traces to govern weight updates. Two neuron-level traces, the postsynaptic trace (post-trace) and the Ca2+ trace, are transmitted to synapses and must meet threshold conditions for weight updates. If the post-trace exceeds a threshold, incoming presynaptic spikes reduce the synaptic weight by a fixed increment. The presynaptic activity (pre-trace) also determines whether the weight will increase or decrease, with updates occurring via charge deposition on a capacitor. The weight is then quantized into high or low states by a bistability circuit, which controls drift toward ground or supply voltage, with drift rates set by the slew up and slew down biases.
