Fig. 4: Spectre post-layout simulations of the read protocol for the differential normalizer synapse on TEXEL.
From: A neuromorphic processor with on-chip learning for beyond-CMOS device integration
a A read pulse with a width of 500 μs activates the normalizer circuit, sourcing Ineg and Ipos. The circuit outputs a non-zero current, Inorm, if Ipos > Ineg, which is integrated by a DPI synapse, resulting in a current Isyn sent to the neuron. The left panel shows high weight storage (Rpos < Rneg), eliciting a response, while the right panel shows low weight storage (Rneg < Rpos), where no current is integrated. b With Rpos = 1GΩ, device capacitance of C = 100 fF, and a read pulse width of 500 μs, the relative resistances of both devices are varied by sweeping Rneg. The average output current of the normalizer circuit is measured as a % of norm_bias, showing non-zero current when the positive device’s conductance exceeds that of the negative device. c Simulations explore device characteristics’ impact on compatibility with TEXEL. The cross ( × ) represents a device with C = 100 fF, Gon/Goff = 100, Ron = 1 GΩ, and a read pulse width of 500 μs. Heatmaps indicate average current from the normalizer as a percentage of norm_bias. d A sweep of the device’s capacitance versus its on/off ratio is shown with Ron fixed at 1 GΩ.
