Fig. 5: Spectre simulation of the differential normalizer synapse integrated with a VCM device compact model.
From: A neuromorphic processor with on-chip learning for beyond-CMOS device integration
a Potentiation (POT) and depression (DEP) events arriving at the synapse execute the complementary set and reset of the two devices in the differential configuration. Presynaptic spikes arriving at the synapse read the state of the devices through the normalizer circuit and the rescaled current is integrated by a DPI circuit providing an EPSC, Isyn, to the associated neuron. Sequential POT and DEP events cycle the weight stored by the synapse, with presynaptic spikes occurring between cycles. b During the cycling of the state of the differential normalizer synapse, the current sourced through the DPI synapse circuit during a presynaptic spike was integrated to calculate the synaptic charge conveyed to the neuron. The distribution of this charge for high and low weight storage is shown, attributed to the cycle-to-cycle variability simulated in the compact model of the memristive device.
