Fig. 8: The footprint and schematic of the per-synapse device interface terminals and schematic of the differential normalizer circuit.
From: A neuromorphic processor with on-chip learning for beyond-CMOS device integration
a A diagram illustrating the physical dimensions and spatial arrangement of the source, drain, and gate contacts for two- or three-terminal devices. Each synapse deploys two devices configured differentially, serving as both positive and negative components. The diagram also provides information on the spacing between synaptic rows, depicting the distances between adjacent devices in each synapse. b Schematic of device interface circuitry. All voltages can be set in the range 0 V to 5 V in order to read or write both devices in the differential configuration. c The differential normalizer circuit functions to compare the currents generated by positive and negative devices during a device read, prompted by a presynaptic spike. It evaluates the disparity between these currents and generates an output current, denoted as Inorm, which is proportional to the normalized discrepancy between Ipos and Ineg. Moreover, Inorm is exclusively non-zero when Ipos surpasses Ineg and can be modulated by the bias norm_bias. Consequently, the output represents the binary state of the synapse, and the sourced current is directed towards a DPI circuit for further processing.
