Fig. 3: High-performance MoS2 transistors with MoO3 as top-gate dielectric.
From: Controllable growth of MoO3 dielectrics with sub-1 nm equivalent oxide thickness for 2D electronics
a Schematic illustration of the top-gate field effect transistor (FET) with as-grown MoO3 as gate dielectric and MoS2 as channel, the TG, S and D are represented as top-gate, source and drain, respectively. b Scanning electron microscopy (SEM) image of the device with MoO3 thickness of 9.31 nm, blue and orange dashed lines represent MoO3 and MoS2 respectively. c Cross-sectional transmission electron microscopy (TEM) image of the MoO3 layer stacked on MoS₂ channel, showing a clean and damage-free interface. d High-angle annular dark-field (HAADF) and corresponding energy-dispersive X-ray (EDX) mapping images for the Mo, O, S, and C elements, confirming the anticipated MoO3/MoS2 structure with distinct elemental distributions. e Transfer characteristics for channel current (IDS) and top-gate voltage (VTG) of the devices with MoO3 thickness from 9.31 nm to 210 nm at drain voltage (VDS) = 1 V. f Transfer characteristics (IDS–VTG) of the transistor with MoO3 thickness of 9.31 nm and the channel length/width of 4.2/2.2 μm measured at different VDS. g Comparison of gate leakage current (LC) density and subthreshold sweep across devices with varying dielectric thicknesses after 2 months.
