Ambipolar ohmic contact to silicon for high-performance brain-inspired image sensors

Abstract

Recently, ambipolar semiconductor devices have excelled in developing programmable photodiodes for brain-inspired image sensors, offering energy, speed, and security gains. However, the lack of mature processing techniques makes their manufacture challenging, and the often-adopted Schottky contacts limit their performance. Although CMOS technology is successful in integrated circuits, the employed ohmic contacts can only transport one type of carriers, failing to meet the requirement of electrons and holes working simultaneously in ambipolar devices. Here we propose an ambipolar ohmic contact to Si via a devised complementary ohmic contact configuration (COCC), allowing efficient transport of electrons and holes simultaneously. The process is entirely compatible with CMOS techniques, enabling the manufacture of device arrays at a wafer scale. We demonstrate their application for in-memory sensing and computing image sensors that can process optical images on 2-class MNIST and fashion-MNIST datasets, which can implement recognition tasks within 7.3 ns if possible limitations of peripheral circuits are not considered. The COCC is also applied to manufacture other brain-inspired hardware, including reconfigurable convolution kernels, and synaptic and neuron-like circuits.

Introduction

Brain-inspired hardware is promising in energy efficiency and the ability to process massive amounts of increasing data^{1,2,3,4,5,6,7}. In two-dimensional (2D) ambipolar semiconductors, the type and density of majority charge carriers can be controlled by the polarity and magnitude of the electrostatic field⁸. With this principle, programmable photodiodes based on modified ambipolar field-effect transistors (ambi-FETs) can mimic synapses with positive and negative weights, combining photo-sensing with neuromorphic computing^9,10,11, providing a pathway for novel brain-inspired image sensors to process optical images within the analog domain and offering energy, speed, and security gains in edge devices^{10,11,12,13,14,15,16,17}. The operation of such devices involves two types of majority carriers (electrons and holes), requiring the metal and semiconductor contacts to simultaneously transport electrons and holes (Supplementary Fig. 2a). Conventional ohmic contacts can only efficiently transport one type of carriers (electrons or holes, Supplementary Fig. 2b)¹⁸, which cannot be applied to ambipolar devices. Currently, Schottky contacts with moderate Schottky barriers of electrons and holes are usually adopted, which, unfortunately, leads to limited performance because the carriers must overcome their corresponding barriers during transport (Supplementary Fig. 2c)^8,19,20. In addition, despite great efforts, integrating 2D devices still faces challenges including achieving high-quality large-area 2D semiconductors and reliable processes. Moreover, the operation of brain-inspired hardware necessitates the inclusion of peripheral modules^21,22. It is imperative to develop a process to achieve their monolithic integration, as it would enhance the integration density and operating efficiency, and reduce manufacturing costs.

As an ambipolar semiconductor, Si dominates the development of integrated circuits (ICs) owing to its mature complementary metal oxide semiconductor (CMOS) technology. In CMOS processes, high doping of Si in contact can thin the width of Schottky barriers between the metals and Si, making the current across the contact dominated by quantum tunneling of majority carriers in the doping area. In this case, the contact resistance can be neglected relative to the whole resistance of devices and the contacts become ohmic contacts (Supplementary Fig. 2b). This can significantly improve the devices’ performance because the voltage drop across the contacts can be neglected relative to that across the active region¹⁸. However, due to the Si in contact only containing one type of majority carriers (electrons or holes), conventional ohmic contacts can only efficiently transport one type of carriers, which cannot be applied to Si ambipolar devices.

To address these challenges, here we propose an ambipolar ohmic contact to Si and demonstrate a pathway to realize it through a complementary ohmic contact configuration (COCC), which is entirely compatible with the CMOS process and facilitates the efficient transport of holes and electrons simultaneously. Based on the COCC and mature Si techniques, wafer-scale devices, including programmable p-n junction photodiodes and programmable nonvolatile p-n junction photodiode memories, have been successfully produced, accompanied by a significant improvement in electrical and optoelectrical properties. Using the programmable nonvolatile p-n junction photodiode memories, an in-memory sensing and computing image sensor is demonstrated to recognize images, which can implement recognition tasks within 7.3 ns if the possible limitations of peripheral circuits are not considered. The demonstrated process is completely based on the current Si technology, which can be monolithically integrated with CMOS circuits, potentially advancing the industrialization of image and related brain-inspired hardware.

Results

Ambipolar ohmic contact to Si

Figure 1a illustrates the design of the COCC for the ambipolar ohmic contact, where the Si in contact consists of a couple of neighboring highly doped n-type (n⁺⁺) and p-type (p⁺⁺) subareas. This results in the Si in contact containing two types of high-density majority carriers (electrons and holes), forming a complementary contact configuration to simultaneously thin the Schottky barriers of electrons and holes, allowing both of them to efficiently quantum tunnel into the same Si channel. Therefore, the COCC can efficiently transport both electrons and holes without any operation, achieving the ambipolar ohmic contact and enabling the manufacture of high-performance ambipolar devices such as programmable p-n junction diodes^10,20 and memories^9,12,13. For device applications, the n⁺⁺ and p⁺⁺ subareas are devised with a centrosymmetric configuration as shown in Fig. 1a. Compared to the axisymmetric configuration, this configuration is much less affected by the punch-through effect caused by the reduction of the gate length, enabling it more conducive to device miniaturization (Supplementary Fig. 3e, f).

Fig. 1: COCC-engineered ambipolar ohmic contact to Si.

a Schematic of the COCC. b Length-dependent total resistance (R_Total-L) of the COCC. Inset: Photography image of the device for measurement. Scale bar, 20 µm. c False-colored SEM image of a typical Si COCC-FET. Scale bar, 50 µm. Inset: Device schematic. d Gate-voltage-dependent whole device resistance (R_Whole-V_G) and proportion of the contact resistance and whole device resistance (R_C/R_Whole-V_G) curves of the COCC-FET at V_D = 0.1 V.

We examined the specific contact resistivity of the COCC with the transmission line model. It was achieved by fabricating parallel Au/Ti electrodes with different gaps on a Si strip, where the strip consists of a couple of neighboring n⁺⁺/p⁺⁺ (width: 10 µm/10 µm) substrips (see details in Methods). Figure 1b shows the dependence between the total resistance (R_Total) and the length (L) of gaps, where R_Total includes the highly-doped Si resistance (R_Strip) and contact resistance (R_C). The intercept of the fitted line with the Y-axis corresponds to the value of 2R_C. The result indicates that the specific contact resistivity, equaling the product of the contact resistance and area, is 5.4×10⁻⁵ Ω·cm², a typical value of the ohmic contacts based on the quantum tunneling effect of high-density majority carriers in Si¹⁸. In addition, we studied the temperature-dependent current-voltage (I-V) curves across the COCC (Supplementary Fig. 4), confirming that the contact is dominated by the quantum tunneling effect of majority carriers.

The ambipolar ohmic contact was further confirmed by manufacturing COCC-engineered FETs (COCC-FETs). Figure 1c displays the scanning electron microscopy (SEM) image of a typical device, and Supplementary Fig. 5 shows the corresponding transmission electron microscopy (TEM) images. The COCC-FETs have a top-gated configuration, in which the channel is 5 µm in length and 20 µm in width, the source/drain (S/D) include centrosymmetric n⁺⁺ and p⁺⁺ subareas (width: 10 µm/10 µm), and the gate dielectric is HfO₂ (thickness: 10 nm). The COCC-FETs exhibit an excellent ambipolar transfer characteristic with on/off ratios of ~10⁶ in both the n-branch and p-branch (Fig. 1d). When the gate voltage (V_G) is scanned from +3.0 to −3.0 V, the whole device resistance (R_Whole) first increases and then decreases with the peak point (charge neutral point) close to V_G = 0 V. It indicates that the variation of the majority carriers in the channel matches well with V_G. When V_G > 0 V, the transport is dominated by electrons, and when V_G < 0 V, it becomes holes. It is worth noting that the on-current resistance of the n-branch at V_G = + 3 V is slightly smaller than that of the p-branch at V_G = −3 V (0.8×10⁴ and 1.5×10⁴ Ω), which should be due to the smaller effective mass of electrons relative to holes. This mismatch can be addressed by meticulously designing the COCC (Supplementary Figs. 3c and 3d). The R_C/R_Whole-V_G curve indicates that the proportion of the R_C to R_Whole is less than 10⁻³ in the linear regions in both the n-branch and p-branch. This means that the contact resistance can be neglected relative to the whole resistance of the COCC-FET whether in electron transport or hole transport, confirming that the COCC achieves the ambipolar ohmic contact to Si. The ambipolar ohmic contact to Si was also confirmed by simulations. As shown in Supplementary Fig. 3b, whether V_G > 0 V or V_G < 0 V, the voltage drop across the contact can be neglected relative to the drain voltage V_D. From the above results, we can conclude that the COCC has the ability to efficiently transport electrons and holes simultaneously, as the Si in the complementary contact contains two types of high-density majority carriers. This is completely different from the Schottky contacts and the conventional ohmic contacts. The former simultaneously suppresses the transport of two types of carriers, and the latter only transports one specific type of carriers (electrons or holes). It should be noted that the ambipolar behavior in the COCC-FETs would increase unwanted leakage current and result in higher power consumption than conventional CMOS-based ICs, which is not conducive to their application in ICs with conventional architectures. However, the COCC can be used to fabricate ambipolar ohmic contact in new-principle ambipolar-operating devices like programmable p-n junction photodiodes and memories for new architecture hardware.

Programmable Si p-n junction photodiode

The manufacture of the COCC only involves techniques including photolithography, ion implantation, metal deposition, and thermal annealing, all of which are mature in Si technology and compatible with CMOS processes, enabling the manufacture of Si ambipolar device arrays at a wafer scale (Fig. 2a). Figure 2b shows the photography images and device schematic of the manufactured double-semi-gate FETs (DSG-FETs), which can be developed for programmable p-n junction photodiodes for in-sensor computing image sensors^10,11. The device layers of the DSG-FETs are similar to those of the COCC-FETs, except that the single gate is replaced by two split semi-gates (SG1 and SG2). During the measurement, the voltages on the two semi-gates are set to V_SG1 = −V_SG2. In the DSG-FETs, each semi-gate locally modulates the type and density of majority carriers in its corresponding portion in the channel by the polarity and magnitude of gate voltages (Supplementary Fig. 6). For example, a negative V_SG1 makes the portion under the SG1 accumulate holes. At the same time, a positive V_SG2 causes the portion under the SG2 to be dominated by electrons. In this case, a lateral p-n junction diode is achieved along the semiconductor channel. When the polarity of V_SG1 = −V_SG2 changes, the channel transforms into an n-p junction diode. Such modulation was verified by the I_D-V_D curves at different V_SG1 = −V_SG2 (Fig. 2c). When V_SG1 = −V_SG2 = 0 V, the device exhibits a typical semiconductor behavior. However, when V_SG1 = −V_SG2 = −1.0 V, it demonstrates a rectification behavior of the p-n junction diode, and when V_SG1 = −V_SG2 = + 1.0 V, the rectification direction becomes reversed, as the built-in electrical field of the n-p junction diodes is reverse to the p-n junction diodes.

Fig. 2: Electrical and optoelectrical characteristics of the programmable p-n junction photodiodes based on the DSG-FETs.

a Photography image of a 4-inch SOI wafer with COCC-engineered device arrays. b Photography image of a DSG-FET array. Scale bar, 200 µm. Upper inset: Schematic of the DSG-FETs. Lower inset: False-colored SEM image of a typical DSG-FET. Scale bar, 50 µm. c I_D-V_D curves of a typical DSG-FET at different V_SG1 = −V_SG2. d Transfer curves of the DSG-FET at V_D = ± 0.5 V. Inset: Corresponding rectification ratio curve dependent on V_SG1 = −V_SG2. e I_D-V_D curves of the DSG-FET under the light illumination with different power densities, where the device is programmed as a p-n junction photodiode by V_SG1 = −V_SG2 = −1.0 V. f I_SC-V_SG1 = −V_SG2 curves of 50 DSG-FETs under the light illumination of 117.6 mW/cm². The highlighted line is the average value.

Figure 2d shows the transfer curves of the DSG-FET at V_D = ± 0.5 V. It can be observed that when V_SG1 = −V_SG2 < 0 V, the current at V_D = + 0.5 V is larger than that at V_D = −0.5 V, while when V_SG1 = −V_SG2 > 0 V, the current at V_D = + 0.5 V becomes smaller than that at V_D = −0.5 V. This is because that V_D = + 0.5 V is a forward bias for the p-n junction diode and becomes a backward bias for the n-p junction diode, vice versa for V_D = −0.5 V. The inset in Fig. 2d displays the dependence between the rectification ratio and V_SG1 = −V_SG2, where the rectification ratios are acquired by comparing the absolute current values of V_D = ± 0.5 V at different specific V_SG1 = −V_SG2. The result exhibits that the rectification ratio can be continuously modulated from 10⁵ to 1, and then from 1 to 10⁵. As the rectification of the p-n junction diodes is determined by the built-in electrical field, this indicates that if the built-in electrical field of the p-n junction diodes is assumed to be negative, the built-in electrical field in the DSG-FETs can be continuously modulated from negative to positive. It is worth noting that the rectification behavior of our DSG-FETs is excellent, with a rectification ratio of more than 5000 times that of similar Si devices with Schottky contacts²⁰, indicating the advantage of our ambipolar ohmic contact.

The optoelectrical properties of the DSG-FETs were examined. As shown in Fig. 2e, when the device is programmed as a p-n junction diode by V_SG1 = −V_SG2 = −1.0 V and under a 685 nm laser illumination, the I_D-V_D curve shifts downwards with the light power density (P/A, P denotes the light power on the device and A is the device area) increasing, indicating photovoltaic energy conversion occurs, and it can be used for self-powered photodetectors. External quantum efficiency (EQE) denotes the ratio of the number of collected charge carriers to the incident photons. Our investigation exhibits that an EQE of 60.24% is obtained. Further study demonstrates that the device is up to 0.74 in fill factor (n) and 8.56% in electrical power conversion efficiency (Supplementary Table 1). Supplementary Fig. 7 and Table 2 display the photovoltaic properties of the device programmed by V_SG1 = −V_SG2 = + 1.0 V, which are similar to the p-n junction diode except that it becomes an n-p junction diode. For light sources, besides the laser, other light sources such as fluorescent lamps and smartphone flashlights can also be used (see Supplementary Fig. 8).

The continuous modulation ability of the built-in electrical field in our DSG-FETs enables the continuous programmability of the short-circuit photocurrent (I_SC) and thus the continuous programmability of the photoresponsivity (R_P = I_SC/P). Figure 2f plots the I_SC-V_SG1 = −V_SG2 curves acquired from 50 DSG-FETs, where the light power density is fixed at 117.6 mW/cm², hence R_P is proportional to I_SC, validating that the value of I_SC can be continuously programmed from negative to positive by V_SG1 = −V_SG2. The statistic exhibits that I_SC varies from −282.5 ± 21.0 to 290.0 ± 16.5 pA/μm as V_SG1 = −V_SG2 are scanned from −1.0 to +1.0 V, indicating the uniformity of the DSG-FETs is excellent, which can be attributed to the mature processes of Si. It is worth noting that if the channel width is normalized, the photoresponsivity of our diodes is almost 100 times that of similar Si devices with Schottky contacts²⁰, once again demonstrating the advantage of our ambipolar ohmic contact. Supplementary Fig. 9 shows the value of I_SC at different V_SG1 = −V_SG2 with the light power density fixed, exhibiting that I_SC, i.e. R_P, can be programmed into multiple states by controlling the polarity and magnitude of gate voltages. As the DSG-FETs are not memories, here specific V_SG1 = −V_SG2 are required to maintain the corresponding states during the measurement. Moreover, our result demonstrates that I_SC at certain V_SG1 = −V_SG2 is linearly dependent on the light power P (Supplementary Fig. 10). Our devices, as electrically programmable photodiodes for light detection, show outstanding endurance in the photoelectric switch and the electrically programming of the photoresponse. After more than 5000 seconds of 10⁴ photoelectric switching and electrically programming cycles, no significant performance degeneration is observed in the devices (Supplementary Fig. 11). In addition, as yield is one of the critical metrics for scalable manufacturing of devices, we evaluated the yield according to the criteria of the tunable range of the photoresponsivity deviation less than ±20%. Supplementary Fig. 12 shows the statistical result based on 50 DSG-FETs, indicating that the tunable range of the photoresponsivity is between 450 and 530 mA/W with an average value of 488 mA/W and a yield is almost 100%, further demonstrating the advantage of our manufacturing process.

Programmable non-volatile Si p-n junction photodiode memory

To manufacture memories, we used ferroelectric Hf_0.5Zr_0.5O₂ (HZO, 20 nm in thickness, its ferroelectricity was confirmed by the electrical field dependent polarity and current hysteresis loops in Supplementary Fig. 13) to replace HfO₂ as the dielectric layer to manufacture ferroelectric DSG-FETs (DSFeG-FETs, Fig. 3a). Unlike HfO₂, the ferroelectricity of the HZO allows to maintain polarization after removing gate voltages, enabling the development of ferroelectric FETs (Fe-FETs) for programmable non-volatile memories. As shown in Fig. 3a, the DSFeG-FETs can be programmed into p-n junction diodes and n-p junction diodes by controlling the polarity of the gate voltage pulses (V_SG1,Pulse = −V_SG2,Pulse, pulse width: 5 µs), in which positive gate voltage pulses align the ferroelectric polarization vector towards the semiconductor channel and make electrons accumulated in the corresponding Si portion, vice versa for negative voltage pulses (Supplementary Fig. 14). The rectification ratio, determined by the built-in electrical field, can be modulated by the magnitude of the voltage pulses and reaches up to 10³ at V_SG1,Pulse = −V_SG2,Pulse =±8.0 V (Fig. 3b and Supplementary Fig. 15).

Fig. 3: Electrical and optoelectrical characteristics of the programmable non-volatile p-n junction photodiode memories based on the DSFeG-FETs.

a I_D-V_D curves of a typical DSFeG-FET at different V_SG1,Pulse = −V_SG2,Pulse. Inset: Schematic of the DSFeG-FETs. b I_D-V_D curves of the DSFeG-FET at different V_SG1,Pulse = −V_SG2,Pulse < 0. c I_D-V_D curves of the DSFeG-FET under the light illumination with different power densities, where the device is programmed as a p-n junction diode by V_SG1,Pulse = −V_SG2,Pulse =−8.0 V. d I_SC of the DSFeG-FET at different V_SG1,Pulse = −V_SG2,Pulse under the light illumination of 117.6 mW/cm². e I_SC-P relationship of the DSFeG-FET at different V_SG1,Pulse = −V_SG2,Pulse. f Retention performance of the DSFeG-FET working in different photodiode modes.

When working as photodiodes, the DSFeG-FETs can convert the incident light into electrical power, where I_SC and V_OC increase with the light power density increasing (Fig. 3c, and Supplementary Fig. 16, Table 3, and Table 4). As displayed in Supplementary Fig. 17, these devices can respond to light across a broad wavelength ranging from 365 to 1045 nm. In addition, the DSFeG-FETs exhibit an excellent electrically programming ability of the photoresponse. The I_SC, i.e. R_P, can be programmed into 12 memory states by controlling the polarity and magnitude of V_SG1,Pulse = −V_SG2,Pulse, where the value of I_SC is about 200 pA/µm at V_SG1,Pulse = −V_SG2,Pulse = ±8.0 V and under the light illumination of 117.6 mW/cm² (Fig. 3d and Supplementary Fig. 18). These 12 memory states are distinguishable at the light power densities as low as 2.7 mW/cm² (Supplementary Fig. 19). Benefiting from the progressive switch of ferroelectric domains, more intermediate-photoresponsivity memory states can be achieved by applying gate voltage pulse series (Supplementary Fig. 20). Moreover, I_SC is linearly dependent on the light power at different V_SG1,Pulse = −V_SG2,Pulse (Fig. 3e). The DSFeG-FETs exhibit excellent endurance in photoelectric switch and electrically programming of the photoresponse, the performance of which maintains well after more than 5000 seconds of 10⁴ photoelectric switching cycles and 10⁵ electrically programming cycles (Supplementary Fig. 21). As memories, they are also excellent on performance retention. After being programmed by voltage pulses, no significant I_SC degeneration is observed after 3000 seconds whether the device works in a p-n junction photodiode mode or an n-p junction photodiode mode (Fig. 3f), confirming the excellent non-volatile ability of the DSFeG-FET memories. We further evaluated the yield according to the criteria of the tunable range of the photoresponsivity deviation less than ±20%. As shown in Supplementary Fig. 22, the statistic indicates that the tunable range of the photoresponsivity is between 260 and 380 mA/W with an average value of 327 mA/W and the yield is 100%.

Ultrafast in-memory sensing and computing image sensor

In-memory sensing and computing image sensors aim at eliminating the walls among photo-sensing, storage, and computing modules by implementing these functions at the pixel level and in the analog domain. This requires that the devices for the pixels can be programmed and maintained at various negative and positive photoresponsivity states and the generated photocurrents are linearly dependent on the incident light power, so that the composed hardware can employ the photoresponsivity states as synaptic weights to perform the high-fidelity analog multiplication of the matrix-vector of light input and electrical output^20,22. Our result demonstrates that the developed DSFeG-FETs can well meet these requirements. Moreover, compared with other memories like floating-gate FETs, ferroelectric FETs are usually advantageous in operating speed and device architecture. Here we show the feasibility of manufacturing high-performance in-memory sensing and computing image sensors with our DSFeG-FETs. Figure 4a shows the layout and working principle. The image sensor consists of N pixels, with each pixel consisting of M photoactive sub-pixels (DSFeG-FETs), which are arranged on the focal plane in the imaging system. All the m-th sub-pixels are connected in parallel to a terminal for the collection of current I_m (m = 1, 2, …, M). When an optical image is projected onto the sensor, the n-th pixel is illuminated by light with a power (P_n) decided by the optical image (n = 1, 2,…, N). The m-th sub-pixel in the n-pixel thus generates a photocurrent (short-circuit current I_SC-mn=R_mn×P_n), where R_mn is its photoresponsivity. According to Kirchhoff’s law, ${I}_{m}={\sum }_{n=1}^{N}{I}_{{mn}}={\sum }_{n=1}^{N}{R}_{{mn}}{P}_{n}$. In this way, the DSFeG-FET network can perform the matrix-vector product operation

$${{\bf{I}}}=\left(\begin{array}{c}{I}_{1}\\ {I}_{2}\\ \begin{array}{c}\vdots \\ {I}_{M}\end{array}\end{array}\right)=\left(\begin{array}{ccc}{R}_{11} & {R}_{12} & \begin{array}{cc}\cdots & {R}_{1N}\end{array}\\ {R}_{21} & {R}_{22} & \begin{array}{cc}\cdots & {R}_{2N}\end{array}\\ \begin{array}{c}\vdots \\ {R}_{M1}\end{array} & \begin{array}{c}\vdots \\ {R}_{M2}\end{array} & \begin{array}{c}\begin{array}{cc}\ddots & \vdots \end{array}\\ \begin{array}{cc}\cdots & {R}_{{MN}}\end{array}\end{array}\end{array}\right)\left(\begin{array}{c}\begin{array}{c}{P}_{1}\\ {P}_{2}\end{array}\\ \vdots \\ {P}_{N}\end{array}\right)=R{{\bf{P}}},$$

(1)

where R = (R_mn) is the photoresponsivity matrix, P = (P₁, P₂, …, P_N)^T is the vector representing the projected optical image, and I = (I₁, I₂,…, I_M)^T is the output vector for inferences. Based on the linear dependence between the input light power and I_SC, via respectively utilizing the negative and positive photoresponsivities of the DSFeG-FETs as the negative and positive synaptic weights, the network can implement artificial neural networks (ANNs) for image processing by locally storing the weights in the photoresponsivity matrix. For example, it can recognize images on MNIST and fashion-MNIST datasets (Supplementary Fig. 23).

Fig. 4: Implement a DSFeG-FET array for the ANN in-memory sensing and computing image sensor.

a Layout and working principle of the ANN image sensor. b Photography image of a manufactured ANN sensor. Scale bar: 200 µm. c Images in the MNIST and Fashion-MNIST datasets and their corresponding processed images with a bilinear interpolation. d Measured output currents and non-linearly activated results of the projected images. e Time-resolved output current for recognizing “1”.

As a demonstration, we manufactured an in-memory sensing and computing image sensor to constitute an ANN to recognize images on 2-class MNIST and fashion-MNIST datasets. Figure 4b displays the photography image of the sensor based on a 7×7 pixel array, with each pixel consisting of one sub-pixel (DSFeG-FET). The images from MNIST and fashion-MNIST datasets are preprocessed into a 7×7 dimensional format via a bilinear interpolation (Fig. 4c), followed by acquiring the optimized weight matrices by a supervised learning algorithm (Supplementary Fig. 24). The optimized weight matrices are subsequently transported into the array by setting the corresponding photoresponsivities of DSFeG-FETs with voltage pulses. Detailed process can be found in Methods. Figure 4d shows typical measured output currents and the corresponding non-linearly activated outputs with the Sigmoid function when optical images are projected onto the sensor, indicating that the images can be well recognized. Figure 4e and Supplementary Fig. 25 display transient output currents for the recognition of images. They demonstrate a resolved time of no more than 7.3 ns with a rise and fall time of no more than 1.2 ns and 4.9 ns, respectively, which is the fastest among all reported in-sensor computing image sensors as far as we know (Supplementary Table 5).

Although machine vision technology has achieved great success²³, it suffers from excessive time delay and energy consumption due to data conversion and shuttle among frame-based cameras, remote processing units, and memories. The ANN in-memory sensing and computing image sensor processes optical images in the analog domain and performs photo-sensing, computing, and memory functions within a single modified FET, eliminating the walls among different modules in conventional architectures. When the images are processed inside the ANN image sensor, the processing speed is limited only by the photoresponse speed of the DSFeG-FETs (the time delay caused by metal interconnection can be relatively neglected). Therefore, an ultrafast recognition speed of the ANN image sensor can be acquired based on our high-performance DSFeG-FETs. In addition, due to the weights being locally remembered in the matrix and the DSFeG-FETs working in a self-powered photovoltaic mode, the energy consumption is zero when optical images are processed inside the ANN image sensor because the synapses of the DSFeG-FETs can convert the incident light into photocurrent without external electrical power required to generate the output current from the synapses during the recognition process. It should be noted that the mentioned speed and energy consumption refer to those of the image sensor when processing tasks inside the ANN image sensor, with no communication and other processing layers or peripheral modules involved. For practical applications, their limitations should be considered. We also studied the speed and energy consumption for the weight updating. The results exhibit an updating speed of 5 µs with an energy consumption of 61.5 pJ (615 fJ/μm²) per device (Supplementary Fig. 26). The performance of our ANN image sensor is superior to other reported similar devices (Supplementary Table 5).

In addition, the device-to-device variance on the performance of the ANN image sensor should be considered. Supplementary Fig. 27 shows the cumulative probability distribution of 49 DSFeG-FETs with respect to 12 independent photoresponsivity memory states, indicating a little overlap exists between neighboring memory states. We further studied the distribution of the memory states. As shown in Supplementary Fig. 28, the result indicates that the standard deviation (σ) values of these states are less than 15. Based on these statistical results, we evaluated the test accuracies of the ANN image sensor for 2-class MNIST and Fashion-MNIST datasets under different device-to-device variance levels, where the variance is quantified as the average standard deviations of all programmed memory states. As displayed in Supplementary Fig. 29, as the variance level increases, the ANN image sensor requires more training epochs to achieve saturation accuracy. Additionally, the recognition accuracy is also affected by the variance levels. As the variance level increases, the recognition accuracy decreases, accompanied by an increasing fluctuation. Notably, when the variance level is less than 20, the influence on the recognition accuracy is slight and can be neglected.

Other brain-inspired hardware

The ambipolar ohmic contact and COCC process can be applied to manufacture multiple brain-inspired hardware. In addition to the above-mentioned ANN image sensor, the DSFeG-FET array can be designed for a reconfigurable convolution kernel to smooth out noises and sharpen enhanced edges for feature capturing by sliding over the images (Supplementary Fig. 30)^13,14,15,20. The technique can also be used to manufacture basic elements to perform neuromorphic computing functions, for example, long-term synaptic plasticity functions of the long-term potentiation (LTP) and long-term depression (LTD) (Supplementary Fig. 20), and short-term synaptic plasticity functions of the paired-pulse facilitation (PPF) and paired-pulse depression (PPD) (Supplementary Fig. 31). Three DSG-FETs can be integrated with one capacitor into a synaptic circuit to perform reconfigurable spike-timing-dependent plasticity (STDP) and pulse-tunable synaptic potentiation or depression functions (Supplementary Fig. 32), which can greatly save transistors compared to CMOS-based circuits^24,25,26. Two DSFeG-FETs can form a neuron-like circuit with a Sigmoid nonlinear activation function (Supplementary Fig. 33)²⁷.

Discussion

To address the challenges of manufacturing high-performance brain-inspired hardware based on ambipolar semiconductor devices, from the perspective of device physics, we proposed an ambipolar ohmic contact to Si that allows efficient transport of electrons and holes simultaneously; from the perspective of manufacturing techniques, we developed a COCC process that can be used to manufacture Si ambipolar device arrays at a wafer scale. We manufactured DSG-FETs for programmable p-n junction photodiode and DSFeG-FETs for programmable non-volatile p-n junction photodiode memory. We demonstrated their application for multiple brain-inspired hardware, including an ANN in-memory sensing and computing image sensor for image recognition, a reconfigurable convolution kernel for image feature capturing, long-term potentiation (LTP) and long-term depression (LTD), paired-pulse facilitation (PPF) and paired-pulse depression (PPD), synaptic circuits for neuromorphic computing, and a neuron-like circuit with a Sigmoid nonlinear activation function.

This pathway is expected to be feasible in terms of scalability. The COCC process is based on mature Si technology and is compatible with CMOS processes, allowing it to be incorporated into current CMOS process lines for achieving interconnection of large-scale device arrays, as well as the monolithic integration with CMOS-based peripheral modules to improve hardware performance and reduce costs. Although the ANN image sensor can implement image processing tasks, deep neural networks (DNNs) with multiple processing layers are often required to handle complex tasks. In this case, our ANN image sensor can act as independent edge hardware and alleviate the pressure of data transmission and processing for the whole system by removing abundant data during constant communication to the cloud, offering energy, speed, and security gains¹. In addition, it can also be integrated with other processing layers, such as optical analog computing (OAC)²⁸, to manufacture compact DNN hardware.

In addition to developing Si-based brain-inspired hardware, the ambipolar ohmic contact and COCC process can be extended to ambipolar 2D and other semiconductors, expanding the scope of application scenarios. For example, multipliers that implement frequency multiplication in wireless communication typically employ power- and area-hungry filtering and amplification circuits²⁹, XNOR-like matching operation of ternary content addressable memories (CAMs) needs twin complementary circuit branches³⁰, both of which can be achieved with ambi-FETs, greatly saving the number of transistors^31,32. Recently, reconfigurable logic circuits obtained by controlling the polarity of 2D ambi-FETs have been reported for emerging applications such as out-of-the-box secure hardware^24,33,34, which may be advanced by our pathway.

Methods

Manufacture of the devices

All of the devices were manufactured using silicon on insulator (SOI). The device layer of the SOI is 100 nm in thickness, which is slightly doped by boron with a resistivity over 1000 Ω•cm and can be regarded as an intrinsic semiconductor. Taking the COCC-FETs as an example, the process flow is demonstrated in Supplementary Fig. 1. The first step was to define two highly boron-doped (p⁺⁺) blocks in the device layer (width: 10 µm; length: 20 µm). The second step was to define two highly phosphorous-doped (n⁺⁺) blocks (width: 10 µm; length: 20 µm), which were aligned beside the p⁺⁺ ones. Both the boron and phosphorous dopants were implemented by a standard ion implantation technique with a dose of ~5×10¹⁵, followed by annealing at a temperature of 1050 ^oC for 60 seconds, resulting in highly doped areas with doping densities of ~10²⁰ cm⁻³. The four implanted blocks are divided into two couples. Each couple includes one p⁺⁺ and one n⁺⁺ block with the configuration shown in Supplementary Fig. 1b (gap width: 20 µm, length: 5 µm). The third step was to isolate the devices, where the surrounding area was firstly etched by inductively coupled plasma etching (ICPE) with SF₆ and C₄F₈ and subsequently filled by SiO₂ with physical vapor deposition (PVD). The fourth step was to define the source/drain (S/D) electrodes. They were achieved by patterning Au/Ti (50/20 nm) electrodes on the p⁺⁺/n⁺⁺ couples by e-beam evaporator and being treated by a rapid thermal annealing technique at 350 ^oC for 5 minutes. The fifth step was to grow the dielectric layer by atom layer deposition (ALD). For the HfO₂, the thickness is 10 nm, where the precursors are tetrakis-(ethylmethylamino)-hafnium (TEMAH, for Hf) and O₂ plasma (for oxygen), and the deposition temperature is 250 ^oC. The last step was to define the top gate of the patterned Au/Cr (50/10 nm).

For the DSG-FETs, the process is similar to that of the COCC-FETs except that the single gate electrode is replaced by two split semi-gates. The semi-gates are 2/20 µm in length/width with a split gap of 1 µm.

For the DSFeG-FETs, the first to the fourth steps are the same. In the fifth step, 20-nm-thick ferroelectric Hf_0.5Zr_0.5O₂ (HZO) was used to replace HfO₂, which was deposited by ALD at 250 ^oC with the precursors of tetrakis-(ethylmethylamino)-zirconium (TEMAZ, for Zr), TEMAH (for Hf), and O₂ plasma (for oxygen). In the last step, the top gates become tungsten (W, thickness: 80 nm). After the W deposition, an additional rapid thermal annealing at 600 ^oC in the N₂ atmosphere for 30 seconds was required to crystallize the ferroelectric HZO.

For the ANN in-memory sensing and computing image sensors based on the DSFeG-FET array, the process is similar to the DSFeG-FETs. The electrical interconnection among DSFeG-FETs was achieved by patterning metal lines in the corresponding layers.

Device characterizations

Structural and morphological characterizations

The SEM images of the manufactured devices were achieved using a Zeiss Sigma 300 field-emission electron microscope. The cross-sectional specimen for TEM was prepared on a Zeiss Crossbeam 550 L electron beam/focused ion beam (FIB) dual beam electron microscope. The TEM images were collected using a JEOL JEM-ARM200F transmission electron microscope.

Electrical and optoelectrical characterizations

The electrical and optoelectrical characteristics of the manufactured devices were measured with a Keithley 4200-SCS semiconductor analyzer. Except for the low-temperature characterizations, they were carried out at room temperature in the atmosphere. The ferroelectric characteristics of the W-HZO-Si capacitor were measured with a Radiant Premier II ferroelectric analyzer.

Selection of gate voltage pulses for programming multiple photoresponsivity states in DSFeG-FETs

We first measured and obtained the average photoresponsivity of each memory state by applying gate voltage pulses (V_SG1,Pulse = −V_SG2,Pulse, pulse width: 5 µs) across 49 DSFeG-FETs. In this way, we achieved the mapping relationship between the average photoresponsivities and programming gate voltage pulses. Then the network was trained to acquire the optimized weights that are constrained within these average values. Finally, we selected gate voltage pulses to program the devices in the circuits into the corresponding photoresponsivities according to the mapping relationship.

Image recognition

Supplementary Fig. 34 shows the setup that is used to experimentally verify the image recognition ability of our ANN image sensor. The process to obtain the output current for inferences involves 7 sequential steps: (1) An optimized weight (photoresponsivity) distribution is achieved through offline training. (2) The optimized weight (photoresponsivity) distribution is transported into the device array by setting the corresponding photoresponsivity of each DSFeG-FET with selected gate voltage pulses. (3) A spatial light modulator (SLM) is used to simulate images to be recognized. Each cell in the SLM features 256 grayscale levels that correspond to image pixel values ranging from 0 to 255. A specific image like “1” is first loaded into the SLM’s control software, where the grayscale levels of the image pixel information are converted into different voltage levels. The converted voltages are then applied to the corresponding cells in the SLM to modulate their light transmittance to obtain the pattern for simulating the images. (4) Light pulses from a femtosecond laser (pulse width, 120 fs) are expanded by a beam expander and pass through the spatial light modulator (SLM) with simulated images, and then focused onto the device array through a lens. (5) Each device in the array generates a short-circuit photocurrent due to the photovoltaic effect. (6) The generated photocurrents from all the devices are summed according to Kirchhoff’s current law because these devices are connected in parallel together. (7) The summed current is output and collected by an oscilloscope to achieve the transient photoresponse, where the oscilloscope has an internal 1 MΩ input impedance and converts the output current into a voltage signal through Ohm’s Law (V_Out=I_Out×R_Impedance).

Simulations

Simulation on the COCC-FETs

To better understand the contribution of the COCC, a 3D device simulation utilizing TCAD was conducted. The dimensions and doping densities of the simulated device closely mirror those of the manufactured prototype. The slightly p-type doped channel is set to 1×10¹³ cm⁻³ in hole density, 100 nm in thickness (${t}_{{{\rm{SOI}}}}$), 5 µm in length (${L}_{{{\rm{ch}}}}$), and 20 µm in width (${W}_{{{\rm{ch}}}}$). The Si in contact in the source/drain (S/D) electrodes includes one highly-doped boron subarea and one highly-doped phosphorus subarea, which are aligned together. Both of them are 20 µm in length and 10 µm in width, following a Gaussian doping profile with a peak concentration of 1×10²⁰ cm⁻³. The gate structure adopts a metal-gate high-k (MGHK) configuration with a metal gate length of 5 µm, a work function of 4.6 eV, and an HfO₂ layer thickness (${t}_{{{\rm{ox}}}}$) of 10 nm. The whole device is on a buried oxide box layer of 400 nm (${t}_{{{\rm{BOX}}}}$). The simulations are based on the coupled solution of the Poisson equation and electron/hole current continuity equation, incorporated with various physical models to accurately represent the device behavior. The OldSlotBoom bandgap model is used to calculate the intrinsic carrier density. Three models, including the PhuMob, Lombardi, and Canali, are employed to calibrate the carrier mobility. In these models, the PhuMob model accounts for bulk mobility, considering electron-hole scattering and screening of ionized impurities; the Lombardi model is for the degradation of mobility at interfaces due to the scattering of acoustic surface phonons and surface roughness; the Canali model is invoked to consider the high-field velocity saturation effect. The SRH (Shockley–Read–Hall) and Auger recombination models are used for carrier generation and recombination effects. Moreover, the Schenk Band-to-Band Tunneling model is included to describe offset leakage current with an additional generation–recombination process. The simulations also consider the S/D ohmic contact resistance, determined by the SchottkyResist model. To ensure the accuracy of the device model, the parameters of these models are meticulously calibrated through a fitting process that aligns simulated results with experimental data. The simulated results are shown in Supplementary Fig. 3a and 3b. It can be seen that the obtained transfer curve fits the experiment well, and the voltage drops between the source and drain are mainly located in the channel.

Simulation on the practical potential of the COCC

Based on the calibrated model parameters, several further simulations were conducted to reveal the practical potential of the COCC. For the COCC-FETs demonstrated in the paper, the boron and phosphorus subareas share the same width, resulting in a larger electron current in the n-branch. By modifying the ratio of born and phosphorus subarea widths (W_P/W_N), a matching between electron and hole current levels can be achieved, as shown in Supplementary Fig. 3c and d. Besides, a better scaling-down capability benefits from the centrosymmetric COCC compared with the axisymmetric configuration (Supplementary Fig. 3e and f). When the p⁺⁺/n⁺⁺ subareas are in the axisymmetric configuration, the off-state leakage current increases obviously with the scaling-down of channel length, which can be attributed to the source-drain punch-through effect. However, when the p⁺⁺/n⁺⁺ subareas are in the centrosymmetric configuration, one p-n junction and one n-p junction are formed in parallel along the channel between the source and drain when no gate voltage is applied. Both the Si p-n junction and n-p junction are turned off at V_D = 0.1 V (0.1 V is lower than the threshold voltage for the p-n junction, and is the backward bias voltage for the n-p junction), thus the off-state current almost doesn’t increase as scaling down. Furthermore, as shown in Supplementary Fig. 35, the intrinsic or lightly doped Si channel seems critical for the ambipolar carriers’ transport in the COCC, the doping density range of which is sufficient to realize ambipolar characteristics from n-type doping density of 10¹⁶ cm⁻³ to p-type doping density of 10¹⁶ cm⁻³.

Calculation of the specific contact resistivity with the transmission line model

To obtain the specific contact resistivity (denoting the ratio of the voltage drop to current density and equaling the product of contact resistance and area), we first fabricated a Si strip with a length of 100 µm, which is obtained as that for transistors including neighboring p⁺⁺/n⁺⁺-Si (10/10 µm in width) subareas aligned together. Then parallel Au/Ti strip-like electrodes (2 µm in length) were patterned on the fabricated doped Si with a series of gaps of 6 µm, 26 µm, …followed by annealing at 350 ^oC for 5 minutes (see inset in Fig. 1b). From the I-V curves, we acquired the total resistances (R_Total) between the electrodes with different distances (L), which includes the highly-doped Si resistances (R_Strip) and the contact resistances (R_C). The slope of the fitted line between R_Total and L represents the value of R_Strip and the intercept with the Y-axis corresponds to the value of 2R_C. Hence, we got the specific contact resistivity between the Au/Ti and p⁺⁺/n⁺⁺ coupled Si is 5.4×10⁻⁵ Ω∙cm².

Calculation of the photovoltaic parameters

The photovoltaic parameters of the fill factor (FF), external quantum efficiency (EQE), and electrical power conversion efficiency (η_pe) of the programmed DSG-FETs (or DSFeG-FETs) were calculated according to the I_D-V_D curves under light illumination.

The maximum output electrical power (P_EL,max) was acquired from the P_EL-V_D curves (${P}_{{{\rm{EL}}}}={I}_{{{\rm{D}}}}\cdot {V}_{{{\rm{DS}}}}$). The FF was calculated based on the following equation,

$${FF}=\frac{{P}_{{{\rm{EL}}},\max }}{{I}_{{{\rm{SC}}}}{\cdot V}_{{{\rm{OC}}}}},$$

(2)

where I_SC and V_OC are the short-circuit current and open-circuit voltage of the p-n photodiodes, respectively.

As for EQE, which denotes the ratio of the number of collected electrons to the number of incident photons, the computational formula is as follow:

$${EQE}=\frac{{I}_{{{\rm{SC}}}}\cdot h\cdot c}{{P}_{{{\rm{light}}}}\cdot e\cdot \lambda },$$

(3)

where h is the Planck constant, c is the light speed in vacuum, λ and P_light are the light wavelength and the power of the incident light, respectively.

As for η_pe, it is the ratio of the maximum output electrical power (P_EL,max) to the incident light power (P_light). The computational formula is as follow:

$${\eta }_{{{\rm{pe}}}}=\frac{{P}_{{{\rm{EL}}},\max }}{{P}_{{{\rm{light}}}}}.$$

(4)

Calculation of the updating energy consumption per device

We calculated the updating energy consumption per device in the programming process based on the following method: updating weights means resetting the polarization of the ferroelectric HZO in the devices, which includes one erasing process and one writing process. For the erasing process and writing process, the energy consumption E can be calculated based on the equation:

$$E=\frac{{{CV}}^{2}}{2}=\frac{{QV}}{2}=\frac{\int {I}_{{{\rm{G}}}}{dt}\times {V}_{{{\rm{G}}}}}{2}=\frac{\int {V}_{{{\rm{G}}}}\times {I}_{{{\rm{G}}}}{dt}}{2},$$

(5)

where C is the ferroelectric capacitance, and V is the magnitude of the applied voltage pulse. With this method, a gate voltage pulse (V_G = −8.0 V, pulse width: 5 µs) was first applied to align the ferroelectric polarization vector backwards the semiconductor channel, then another gate voltage pulse (V_G = +8.0 V, pulse width: 5 µs) was applied to reverse the polarity. During the process, the gate voltage amplitude (V_G) and current (I_G) including polarization current and leakage current were measured with a pulse measurement unit (PMU) instead of a source measurement unit (SMU), as the PMU can monitor high-frequency electrical signals while the SMU cannot do and will give wrong information. The obtained results are shown in Supplementary Fig. 26. Based on Eq. 5, the calculated energy consumptions are 30.9 pJ (per erasing, 309 fJ/μm²) and 30.6 pJ (per writing, 306 fJ/μm²), respectively. Therefore, the energy consumption per device per update is 30.9 pJ+30.6 pJ = 61.5 pJ (309 fJ/μm² + 306 fJ/μm² = 615 fJ/μm²).