Fig. 1: Description of the C-2DEG FET technology platform and fabrication of insulation channels.
From: Cryogenic in situ fabrication of reversible direct write logic circuits and devices
a A schematic of optical-electric C-2DEG field-effect transistor. b Two-wire method and Van der Pauw method were employed to measure the resistance-temperature curves of the C-2DEG interface, respectively. c Pulsed back-gate voltages ranging from 100 to 210 V with a pulse width of 1 ms were applied to achieve different resistance states of the C-2DEG interface under VDS = 0.5 V. d The ID-VDS curve of normal-off interface exhibits an onset voltage of approximately 2.6 V. The illustration indicates that the interface experiences breakdown at a VDS of around 40 V.
