Abstract
Next-generation semiconductor devices are adopting three-dimensional (3D) architectures with feature sizes in the few-nanometer regime, creating a need for atomic-scale metrology to identify and resolve performance-limiting fabrication challenges. X-ray methods provide 3D information but lack atomic resolution, while conventional electron microscopy offers limited depth sensitivity. Here we show how multislice electron ptychography, a computational microscopy technique with sub-Ångström lateral and nanometer-scale depth resolution, enables 3D imaging of buried device structures. We image prototype gate-all-around transistors and directly quantify roughness, strain, and defects at the interface of the 3D gate oxide wrapped around the channel. We find that silicon in the 5-nm-thick channel relaxes away from the interfaces, leaving only ~60% of atoms in a bulk-like structure. From a single dataset, ptychography provides quantitative metrology of atomic-scale interface roughness in 3D, previously accessible only through indirect inference, along with strain and other structural parameters needed for device modeling and process development.
Data availability
The experimental 4D-STEM datasets, through-focal ADF/iDPC image stacks, and reconstructed multislice electron ptychography (MEP) phase volumes used to generate the figures in this study are publicly available on Zenodo at https://doi.org/10.5281/zenodo.1588244377. Simulation inputs and results are not included in this repository as they are based on third-party structural models62 that are not owned by the authors.
Code availability
The MATLAB reconstruction scripts (fold_slice with tilt-propagator extension), parameter files documenting all acquisition and reconstruction settings, and Jupyter notebooks used for atom tracking, strain mapping, and surface morphology analysis are publicly available on Zenodo at https://doi.org/10.5281/zenodo.1588244377.
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Acknowledgements
S.K., D.A.M. acknowledge funding from TSMC through a Joint Development Project (JDP184087). S.E.Z. acknowledges funding from the Platform for the Accelerated Realization, Analysis, and Discovery of Interface Materials (PARADIM), which is supported by the National Science Foundation under Cooperative Agreement No. DMR−2039380. This work made use of the electron microscopy facility of PARADIM and Cornell Center for Materials Research shared instrumentation facility with Helios FIB supported by NSF (DMR-1539918). The authors also thank Malcolm Thomas, Mariena Silvestry Ramos, Philip Carubia, and John Grazul for technical support and maintenance of the electron microscopy facilities. The authors gratefully acknowledge Michael Givens (ASM), Naoto Horiguchi (imec), Hans Mertens (imec), and Hiroaki Arimura (imec) for providing the Gate-All-Around (GAA) sample used in this study. We thank Jiangtao Zhu and Eurofins Nanolab Technologies for preparing the GAA TEM lamella used in this study. We thank Frieder Baumann for the c-Si/a-SiO2 structural model, Richard Aveyard and Bernd Rieger for the pMOS structural model. S.K. gratefully acknowledges Harikrishnan K.P., Ariana Ray, and Salva Rezaie for training and tutorials on MEP, Dasol Yoon for insightful discussions on multislice simulations, Xiyue Zheng for sharing the automated DPC acquisition code, and Yi Jiang for helpful discussions about MEP. S.K. thanks Lopa Bhatt for developing and sharing a tilt propagator extension to the fold-slice code used in this study.
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The research plan was formulated by S.K., T.K.C., V.D.H.H. and D.A.M. G.W. sourced the studied samples. S.K. performed STEM and MEP characterization and analysis (experimental and simulation) under the supervision of S.E.Z. and D.A.M. S.K. wrote the original draft with feedback from all authors. All authors discussed the results and commented on the paper.
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Cornell University (D.A.M.) has licensed the EMPAD hardware to Thermo Fisher Scientific. The other authors declare no competing interests.
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Karapetyan, S., Zeltmann, S.E., Wilk, G. et al. 3D atomic-scale metrology of strain relaxation and roughness in Gate-All-Around transistors via electron ptychography. Nat Commun (2026). https://doi.org/10.1038/s41467-026-69733-1
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DOI: https://doi.org/10.1038/s41467-026-69733-1
