Abstract
The human brain recalls complete patterns from partial cues via associative memory, but Hopfield neural networks emulating this process are inefficient on conventional hardware, and prior memristor-based implementations are vulnerable to device defects and have limited capacity, particularly for continuous patterns. We introduce a hardware-adaptive learning algorithm that incorporates experimentally calibrated device constraints during training and validate it on an integrated memristor crossbar compute-in-memory platform. The approach improves defect tolerance and effective capacity, achieving threefold higher capacity than a pseudo-inverse baseline at 50% stuck-at faults. The same framework extends to scalable multilayer architectures supporting binary and continuous-valued patterns, where we observe superlinear capacity scaling on correlated data (∝N1.49 and ∝N1.74, respectively). Leveraging crossbar parallelism with synchronous updates, the implementation reduces energy by 8.8× and latency by 99.7% for 64-dimensional patterns versus asynchronous schemes. These results provide a practical algorithm-hardware co-design for robust, efficient Hopfield-style associative recall.
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Data availability
All data supporting this study and its findings are available within the article, its Supplementary Information, and associated files. Source data have been deposited in Figshare at: https://doi.org/10.6084/m9.figshare.31266745.
Code availability
All the necessary codes used in the tactile experiments and visual experiments, and their descriptions, are available on GitHub: https://github.com/hecp2025/SuperlinearAssociativeMemory. The version used for this study has been archived in Zenodo: https://doi.org/10.5281/zenodo.18494623.
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Acknowledgements
This work was supported in part by the Research Grant Council of Hong Kong SAR (17207925 (C.L.), C7003-24Y (C.L.), C1009-22GF (C.L.), T45-701/22-R (C.L.), C500124Y (C.L.)), Innovation and Technology Commission of Hong Kong SAR (MHP/363/24 (C.L.)), MOST (2024YFE0217000 (C.L.)), ACCESS—an InnoHK center by ITC (C.L.), and Croucher Innovation Award from the Croucher Foundation (C.L.).
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C.H. and C.L. conceived and designed the study. C.H. performed the experiments and collected the hardware measurements, developed the training framework, carried out simulations, and analyzed the results. M.J., K.S., S.-H.Y., and Z.L. contributed to technical discussions and project development. S.W. assisted with figure preparation and data visualization. G.P. and J.I. provided hardware/platform support and contributed to technical discussions. C.L. supervised the project. C.H. and C.L. wrote the manuscript with input from G.P. and J.I. All the authors discussed the results and commented on the manuscript.
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He, C., Jiang, M., Shan, K. et al. A hardware-adaptive learning algorithm for superlinear-capacity associative memory on memristor crossbars. Nat Commun (2026). https://doi.org/10.1038/s41467-026-69958-0
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DOI: https://doi.org/10.1038/s41467-026-69958-0
