Fig. 2: Concrete implementation of the noise-resilient Hadamard test.

In this figure, we illustrate how \(U=W\times V={\otimes }_{i = 1}^{{N}_{W}}{W}_{i}\times {\otimes }_{i = 1}^{{N}_{V}}{V}_{i}\) mentioned in Theorem 1 can be implemented in a noise-resilient manner. The coherently controlled unitaries with a blue contour implement the controlled Hermitian unitaries W_i, which overall implement the controlled W. The coherently controlled unitaries with a black contour implement the controlled V_i, which overall implement the controlled V. The central element in this construction is the parallelization register⁶⁸, which allows the implementation of the unitary W in such a way that it acts upon all the qubits in the data register while preserving the noise-resilience. Hence, it allows the implementation of a Hadamard test with U acting on all the qubits of the data register. Such unitaries are useful for our benchmarking protocol: see the third paragraph in the discussion section. The key point behind the parallelization register is that, while it introduces additional components that can introduce bit-flip errors, these bit-flips cannot, by construction, propagate to the measured register (in practice, they commute with the last c_XX gate drawn, (see the paragraph “Notations and terminology” in the section Results to understand our notations). It is an example where trading space (using more qubits) to gain time (guaranteeing that the measured register interacts with \(O(\log (n))\) gates and not poly(n) gates) is worth doing. While the parallelization register does not propagate bit-flips toward the measured register, it will propagate phase-flip errors. We make use of this to easily detect an excessive production of phase-flip errors in the third paragraph of the discussion section.