Fig. 3: Electronic properties of large-area vdW-integrated monolayer MoS2 FETs with Ag/Au contacts.
From: Highly reproducible van der Waals integration of two-dimensional electronics on the wafer scale
a, Optical microscope image of a short-channel device with 6 nm HfO2 dielectrics. The inset is the corresponding scanning electron microscope image for measuring the length (L) and width (W) of this short-channel device (L = 145 nm; W = 2.8 μm). The short-channel source–drain electrodes are defined by electron-beam lithography. The scale bar in the inset is 2 μm. b,c, Output characteristics (b) and transfer characteristics (c) of the short-channel devices. The IDS, VDS and VGS represent source–drain current, source–drain voltage, and gate voltage, respectively. d, Transfer characteristics (VDS = 6 V) of 60 randomly selected MoS2 FETs with vdW Ag/Au contacts and 60 randomly selected devices with deposited (evaporated (Evap.)) Ag/Au contacts with 12 nm Al2O3 dielectrics and a channel width/length (W/L) of 8/6 μm. e–i, The statistical distribution of Vth (e), Ion (f), Ioff (g), the on/off ratio (h) and SS (i) at room temperature. The Vth is threshold voltage.
