Main

Two-dimensional (2D)semiconductors such as molybdenum disulfide (MoS2) have attracted intensive interest for novel device applications1,2,3. In contrast to three-dimensional (3D) bulk semiconductors, 2D semiconductors feature an atomically thin geometry and dangling-bond-free surface. They could exhibit excellent electronic properties at the subnanometre thickness limit and superior immunity to short-channel effects to give the ultimate transistor scaling in the regime of sub-10 nm gate length4,5. In particular, MoS2 transistors with 1 nm gate length exhibit excellent switching characteristics with a nearly ideal subthreshold swing (SS) of ~65 mV dec–1 (ref. 6), highlighting the considerable potential of 2D semiconductors in continued transistor scaling.

For the realization of practical industrial applications, the scalable synthesis of 2D semiconductors and industry-compatible fabrication of high-performance transistors are essential3,7,8. Encouragingly, the large-area wafer-scale synthesis of monolayer 2D semiconductors9,10, especially semiconducting transition metal dichalcogenides, has recently been achieved by a solid-source chemical vapour deposition (CVD)11,12 or metal–organic CVD13 process.

Wafer-scale integration of 2D transistors has also been realized using a conventional lithography and metallization process; however, this process often has a large device-to-device variation, and the overall performance (for example, the on-current value) is typically about one order of magnitude lower than that of the best research devices14. A key challenge for fabricating high-performance transistors is the formation of high-quality metal–semiconductor contacts15,16,17,18.

Recent studies have shown that bond-free van der Waals (vdW) contacts19,20,21, made by using 2D metals or semimetals22,23,24, 2D/3D hybrid stacks25,26 or 3D metals15,19,20,21,27,28,29, could minimize the interfacial damage and effectively improve the quality of the metal–semiconductor contact15,19. However, most of these approaches are based on non-scalable exfoliated materials30. A potentially scalable indium/gold 3D-metal-based vdW contact has been realized using a standard laboratory electron-beam evaporation process17. Nonetheless, the undesired contamination and damage may still occur during the direct lithography process on the surface of 2D semiconductors16. Alternatively, a modified atomic-layer deposition process has also been used to create vdW metal–semiconductor contacts, yet is still plagued with an undesirable high resistance31. Additionally, the direct chemical deposition growth of large-scale 2D-metal/semiconductor heterostructures may also offer a pathway to scalable vdW integration32, which could be limited to specific material systems.

The vdW integration relies on a physical pick-up-and-place integration process, in which the prefabricated electrodes on the sacrificial substrate are directly peeled off, transferred and laminated onto 2D semiconductors to achieve an atomically clean interface with minimum interfacial damage and nearly ideal pinning-free metal–semiconductor contacts33,34. In a typical vdW integration process3,19,33,34, the vdW metal contacts are typically picked up by a free-standing polymer film and aligned using a soft stamp (for example, silicone polymer). The formation of wrinkles, surface contaminations and interfacial bubbles in the soft polymer stamp could limit the scalability and reliability of these processes. Additionally, such technical challenges further limit the ability to transfer the contacts onto the existing patterned structure with sufficient alignment accuracy, which is necessary for the multilayer lithography and integration process in typical microelectronic fabrications. Such challenges grow exponentially with increasing integration area and steps. These technical challenges have prevented reliable implementation of vdW integration over a large area.

A scalable transfer printing technique has been previously developed for transferring solid objects from a donor substrate to a receiver substrate21,35, for assembling a myriad of materials onto various substrates for flexible electronics, such as curvilinear electronics, deformable opto-electronics and many others36,37,38. Nonetheless, these previous transfer printing efforts usually involve electronically passive interfaces. In this regard, the vdW integration is distinct in that it focuses on creating an atomically clean and damage-free electronic interface that allows efficient charge transport across the transfer-integrated interfaces, which has not been reported for conventional 3D materials until recently19. However, although the vdW integration process has shown tremendous benefits for exfoliated 2D flakes, high-quality vdW integration over a large area, particularly on large-area CVD materials, has not been systematically explored or achieved to date, to the best of our knowledge. Considering that ‘atomic cleanness’ and ‘large area’ are intrinsically traded-off factors, it remains an open question whether the vdW integration can be effectively implemented over a large area to achieve uniform, high-quality electronic interfaces for scalable transistor fabrications.

In this Article, we report an efficient large-area vdW integration process for scalable fabrication of high-performance transistors and logic circuits on a 2-inch wafer of CVD-grown monolayer MoS2. By designing a quartz/polydimethylsiloxane (PDMS) semirigid stamp and adapting a standard photolithography mask-aligner for the vdW integration process, our strategy ensures a uniform mechanical force for precise control of the competing adhesion/separation between the critical interfaces to achieve a bubble-free, wrinkle-free interface. Our approach is compatible with mature industry technology and can be aligned with prepatterned high-dielectric-constant oxide and metal–gate-oxide–semiconductor devices on the 2-inch wafer. The vdW integration approach allows damage-free integration of high-quality contact on monolayer MoS2 to enable 2D transistors with high performance and high reproducibility. The vdW-integrated field-effect transistors (FETs) can readily enable high-performance logic inverters, with the highest voltage gain of up to 585, as well as more complex NOR gates, NAND gates, AND gates and half-adder circuits. These studies demonstrate the scalable vdW integration of 2D transistors and logic circuits on large-area CVD-grown MoS2.

Wafer-scale vdW integration

It has been widely recognized that the conventional lithography process usually introduces a polymer residue on 2D materials and that a direct metallization process would cause uncontrolled damage, such as defects, metal diffusion and chemical bonding, on 2D semiconductors15,17,19 (Supplementary Fig. 1a,d,f). The vdW integration can enable damage-free metal integration on 2D semiconductors and produce nearly ideal metal–semiconductor contacts (Supplementary Fig. 1b,c,e). In this case, the prefabrication of the electrode array can be achieved using a conventional, scalable lithography and vacuum deposition process and can therefore, in principle, be transferred onto wafer-scale 2D materials to enable scalable integration. We have adopted an embedded local back-gate structure to illustrate the large-scale vdW integration process for the fabrication of locally gated 2D transistors and logic circuits (Methods and Supplementary Fig. 2 for more details about the flow of the fabrication process for this vdW integration).

Several critical technical challenges must be addressed to achieve reliable vdW integration over a large area with acceptable interlayer alignment registration, which is necessary for the multilayer processes typically needed for transistor fabrications. In particular, the typical vdW integration involves peeling off and laminating metal electrodes using polymer stamps and thermal release tape. During the process, the formation of wrinkles or air bubbles can seriously undermine the reliability of the process for scalable integration, and can also cause serious challenges for interlayer alignment over a large area (Supplementary Fig. 3a–d).

To this end, we developed a large-scale vdW integration strategy by effectively controlling the vdW forces to realize the pickup, alignment and detachment integration steps (Fig. 1a). First, we used a plasma bonding approach to tightly bind the large-area PDMS stamp with a stiff quartz holder, which is then used for peeling off and picking up the polymethyl methacrylate (PMMA)-encapsulated electrode array (Fig. 1a and Supplementary Fig. 2d). Our unique design of vdW integration with a quartz/PDMS semirigid stamp is optimized for applying a uniform mechanical force with minimum structural deformation and without any lateral sliding between the PDMS and PMMA at their interface to effectively force out all bubbles during the lamination contact process (Fig. 1a and Supplementary Fig. 3e,f). Such a conformal-contact, bubble-free and wrinkle-free interface is essential for ensuring sufficient vdW force between the PDMS stamp and PMMA/metal layer for a high-yield peeling off and picking up of the PMMA/metal layer (Fig. 1a).

Fig. 1: Wafer-scale vdW integration.
figure 1

a, Schematics of large-area vdW integration approach by adapting a contact mask-aligner. b,c, Photograph of 2-inch wafer-scale electrodes on sacrificial substrate (b) picked up by a quartz/PDMS stamp (c). d,e, Photograph of a 2-inch wafer with prefabricated gate electrodes as the receiving substrate (d) and the wafer-scale vdW-integrated device (e).

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Next, we directly aligned the quartz/PDMS/PMMA/metal layers with the target substrate by using two standard alignment markers and using optical microscopy with a customized two-lens transfer platform (Supplementary Fig. 4). Finally, we peeled off the quartz/PDMS stamp by heating the substrate to 120 °C to reduce the vdW force between the PDMS and PMMA, leaving the PMMA/metal on the receiving substrate (Fig. 1a). The analysis of the energy release rate and the finite element analysis are completely coherent with the descriptions of large-area vdW integration (Supplementary Fig. 5a–c and Supplementary Text for more details about the discussion).

Importantly, such an aligned vdW integration process can be readily implemented at the wafer scale (on a 2-inch wafer). A close comparison of the electrode patterns on the sacrificial substrate, on the stamp and on the receiving substrate clearly shows that all of the prepatterned electrode array is fully peeled off from the sacrificial substrate (Fig. 1b), picked up by the quartz/PDMS stamp (Fig. 1c) and transferred onto the receiving substrate (Fig. 1d,e) with a nearly quantum yield. No apparent residue is left on the sacrificial substrate or the quartz/PDMS stamp. A close inspection of the vdW-integrated devices on the receiving substrate across the wafer shows a highly uniform interface with no apparent bubble formation or electrode deformation in the transferred electrodes. Overall, the wafer-scale vdW integration devices can reach a high yield of up to 97.8%. Some 1–2% electrode loss occurs in the multistep fabrication process, with steps including photolithography, the metallized process and the lift-off process, which is not surprising considering that our process is not carried out in a highly controlled clean-room environment. Any particulate contamination can cause slight electrode loss. Such loss can certainly be mitigated when the process is conducted in a more controlled industrial environment. To further highlight the bubble-free and wrinkle-free PDMS–PMMA interface, we captured some pictures (Supplementary Fig. 5d–f) and a video (Supplementary Video 1) that clearly show that all air bubbles can be effectively forced out by the semirigid quartz/PDMS stamp with minimum local structure distortion.

To ensure reliable vdW integration with an atomically clean interface over a large area, it is essential to ensure the atomic smoothness of the underlying MoS2 thin film. To this end, we have extensively characterized the surface and uniformity of the MoS2 film after the transfer process over a large area. Atomic force microscopy (AFM) studies on six randomly selected locations over the large area of the MoS2 surface show a clean surface with a mean surface roughness of ~0.2–0.4 nm, demonstrating the residue-free transfer process. Additionally, the photoluminescence (PL) mapping images over a large area also show highly uniform features that suggest the high quality of the MoS2 film (Supplementary Fig. 6). We further conducted cross-sectional scanning transmission electron microscopy (STEM) studies to closely examine the metal–semiconductor interfaces in MoS2 devices with vdW Ag/Au contacts and deposited Ag/Au contacts. Since it is generally very difficult to achieve high-quality cross-sectional STEM images from monolayer transition metal dichalcogenides, we conducted similar studies on bilayer MoS2. Overall, these cross-sectional STEM studies clearly demonstrate that damage-free vdW interfaces are obtained in both monolayer and bilayer MoS2 FETs with vdW contacts and a 0.2 nm vdW gap (Supplementary Fig. 1c,e). By contrast, for MoS2 FETs with deposited contacts, abundant interfacial defects exist in both the monolayer and bilayer MoS2 (Supplementary Fig. 1d,f), which we believe may partially contribute to device degradation and the large variability in large-scale MoS2 FETs with deposited contacts.

Alignment offsets in vdW integration

We have further analysed the relative position alignment between the vdW-integrated source–drain contacts with respect to the underlying predefined gate electrodes. High-resolution optical microscopy images taken at different locations show that the alignment offsets range from 0 to ~10 μm across the 1 × 1 cm2 chip (Fig. 2a,b). The alignment errors, both for x deviation (Δx) and y deviation (Δy), were carefully measured and analysed (Supplementary Fig. 7a for the definition of positive direction). Overall, the large-area vdW-integrated devices exhibit alignment errors of 2.1 ± 2.5 μm for the x axis and 5.2 ± 2.3 μm for the y axis (Fig. 2c,d and Supplementary Fig. 7b,c). Additionally, the plot of the displacement vector mapping, defined as (Δx, Δy), clearly reveals that the alignment offsets mainly consist of displacement and rotation offset across the entire 1 × 1 cm2 chip (Fig. 2e). These alignment errors originate from the existence of a small slant angle and rotation angle between the transferred electrode layer and the receiving substrate (Fig. 2f). They occur because one side of the quartz/PDMS stamp usually attaches on the substrate first, with a high alignment resolution, limited only by the resolution of optical imaging and the actual alignment (for example, typically about ±2 μm in contact lithography), whereas the other side will be influenced by deviations in imaging attributed to the offset of the focal plane, even when it is well aligned under optical microscopy. Moreover, a slight deformation of the PDMS layer in the transfer platform may also induce a scaling offset and rotation error. For example, a small 0.02° rotation angle could lead to ~4.9 μm displacement across a 1 × 1 cm2 chip, which is very close to our alignment errors. Such a deformation-induced scale offset and rotation error may be further minimized through the development of advanced tools in the industry, such as in electro-optical systems, computer-aided control systems and precision mechanics, by employing a scaling offset compensation process in future studies.

Fig. 2: Alignment offset in large-scale vdW integration.
figure 2

a, Optical microscope image of a 1 cm2, chip-scale vdW-integrated device. The scale bar is 1 mm. b, High-resolution optical microscope images at different locations marked in a. c, High-resolution optical microscope image showing the x axis and y axis alignment offset. The inset shows the areas in the dashed box. d, Statistical distribution of the alignment offset. e, Displacement vector mapping. f, Schematic illustration of the alignment offset analysis. θ, slant angle.

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Uniformity and performance of vdW-integrated MoS2 FETs

We next evaluated the electronic properties of the vdW-integrated MoS2 devices with local back-gate and vdW silver (Ag) contacts. We first evaluated the basic transistor performance of a vdW-integrated MoS2 FET (Fig. 3a). The drain current–voltage (Id–Vd) output curves exhibit linear characteristics at low bias, suggesting satisfactory contact formation. The contact resistance for the vdW Ag contact to monolayer CVD-grown MoS2 is 2.3 kΩ μm, comparable to previously reported vdW contacts (Supplementary Fig. 8). The output characteristics also show clear current saturation, with the highest on-current value of up to 240 μA μm–1 (Fig. 3b), which may be further improved through the optimization of the quality of the CVD-grown MoS2. Transfer characteristics reveal an on/off ratio of up to approximately nine orders of magnitude, with a nearly ideal SS of 77 mV dec–1 and an ultra-low off-state current (Ioff) of ~80 fA μm–1, suggesting few interfacial trapping states in these vdW-integrated devices (Fig. 3c).

Fig. 3: Electronic properties of large-area vdW-integrated monolayer MoS2 FETs with Ag/Au contacts.
figure 3

a, Optical microscope image of a short-channel device with 6 nm HfO2 dielectrics. The inset is the corresponding scanning electron microscope image for measuring the length (L) and width (W) of this short-channel device (L = 145 nm; W = 2.8 μm). The short-channel source–drain electrodes are defined by electron-beam lithography. The scale bar in the inset is 2 μm. b,c, Output characteristics (b) and transfer characteristics (c) of the short-channel devices. The IDS, VDS and VGS represent source–drain current, source–drain voltage, and gate voltage, respectively. d, Transfer characteristics (VDS = 6 V) of 60 randomly selected MoS2 FETs with vdW Ag/Au contacts and 60 randomly selected devices with deposited (evaporated (Evap.)) Ag/Au contacts with 12 nm Al2O3 dielectrics and a channel width/length (W/L) of 8/6 μm. e–i, The statistical distribution of Vth (e), Ion (f), Ioff (g), the on/off ratio (h) and SS (i) at room temperature. The Vth is threshold voltage.

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For further comparison, we also fabricated similar back-gated monolayer MoS2 devices with 12 nm Al2O3 dielectrics to minimize the impact of the evaporation-induced damage to the dielectric layers on the embedded gate. To systematically explore the scalability and uniformity of the vdW integration process, we characterized the electrical properties of the MoS2 transistors with vdW contacts and deposited metal contacts on a 2-inch wafer with the same channel length of 6 μm and width of 8 μm. Transfer characteristics of 60 randomly selected MoS2 FETs with vdW Ag/Au contacts show typical n-type characteristics with excellent uniformity (Fig. 3d). By contrast, large device-to-device variations were observed in transfer curves of 60 MoS2 FETs with deposited Ag/Au contacts (Fig. 3d). A statistics histogram analysis of the threshold voltage shows that the spread of the threshold voltage variation in the devices with deposited contacts (σ = 1.1 V) is about three time larger than that in devices with vdW contacts (σ = 0.4 V), which may be largely attributed to the uncontrolled performance degradation of the monolayer MoS2 during conventional lithography and metal-deposition processes (Fig. 3e).

We further analysed and compared other key parameters. The vdW-contacted devices show a relatively narrow distribution of on-state current (Ion) values of 1.6 ± 0.5 × 10−5 A μm–1, while the devices with deposited contacts show a rather large variation and overall considerably lower Ion (1.0 ± 0.9 × 10−5 A μm–1; Fig. 3f). Although the best devices with deposited metal contacts exhibit comparable Ion values to those with vdW contacts, the uncontrolled damage and defects at the contact in deposited metal contacts lead to large device-to-device variation15,29, with a significant fraction of the devices exhibiting much lower on-currents.

Additionally, the devices with vdW contacts show a low off-state current (Ioff ≈ 1.5 ± 0.6 × 10−12 A μm–1), high on/off ratio (Ion/Ioff ≈ 1.1 ± 0.3 × 107) and relatively small subthreshold swing (SS ≈ 153 ± 45 mV dec–1; Fig. 3g–i). By contrast, the devices with deposited metal contacts show notably higher Ioff (1.2 ± 0.2 × 10−11 A μm–1), smaller Ion/Ioff (9.0 ± 8.3 × 105) and larger SS (248 ± 102 mV dec–1), which can all be attributed to more interfacial trapping states at the contact interface. It has been widely recognized that the vacuum deposition and metallization process can cause considerable defects and charge traps in 2D semiconductors16,28,39. Such interfacial states can lead to a considerably larger leakage current in a reverse-biased metal–semiconductor junction at off states, leading to high Ioff and smaller Ion/Ioff and contributing to additional parasitic capacitance, resulting in a large SS. By contrast, the vdW-contacted devices avoid such process-induced damages to ensure minimum interfacial states, resulting in a high device uniformity, low Ioff, large Ion/Ioff and small SS.

Devices based on vdW-integrated MoS2 FETs

The uniformity and scalability of the vdW-integrated MoS2 FETs can readily enable the fabrication of high-performance logic gates and more complex circuits. Although there have been reports of p-type conversion of MoS2, these studies mainly focused on proof-of-concept demonstrations with exfoliated flakes19,40. To obtain high-performance p-type MoS2 transistors remains a challenge. We constructed an n-type metal–oxide–semiconductor inverter using two locally gated MoS2 FETs with one transistor acting as an active load (Fig. 4a). Importantly, with minimized interface states, the voltage transfer characteristics of the n-type metal–oxide–semiconductor MoS2 inverter show a highly sharp voltage transition at different supply voltage (Vdd) values from 1 V to 5 V (Fig. 4b) with a phenomenal voltage gain of up to 585 (Fig. 4c), which represents the highest voltage gain value ever reported for monolayer MoS2 electronics to date, to the best of our knowledge (Fig. 4d)12,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55. The total noise margin, defined as (NML + NMH)/Vdd, where NMH is the noise margin high and NML is the noise margin low, reaches up to 97% at the Vdd of 5 V, suggesting the high noise tolerance of the vdW-integrated inverter (Fig. 4e). Additionally, all noise margins exceed 80% at various operating voltages, indicating the robustness of the vdW-integrated inverter for multistage operations56 (Fig. 4f).

Fig. 4: Monolayer-MoS2-based inverter with vdW contacts.
figure 4

a, Structural schematics of MoS2 inverter with vdW contacts. The GND, Vin and Vout represent ground, input voltage and output voltage for the inverter, respectively. b,c, Voltage transfer characteristics (b) and the corresponding voltage gain (c) of the vdW-integrated MoS2 inverter. d, Comparison of gain as a function of Vdd with various inverters reported in the literature12,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55. e, Voltage transfer characteristics and their mirror reflection (red line), of the vdW-integrated MoS2 inverter at Vdd = 5 V. The VOH, VOL, VIL, and VIH represent the minimum high output voltage, maximum low output voltage, maximum low input voltage, and minimum high input voltage for the inverter, respectively. The noise margain can be extracted by nesting the largest possible square (grey shading) in the area enclosed by the solid lines. The dashed lines are auxiliary lines for extracting the value of VOH, VOL, VIL, and VIH. f, Total noise margin as a function of Vdd.

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Taking a step further, we also designed and fabricated large-scale logic gate arrays by vdW integration over an 80 mm2 area (Fig. 5a and Supplementary Fig. 9). Importantly, all 576 logic gates were integrated with little alignment offset. The resulting logic NOR gates, NAND gates and AND gates all demonstrate the designed logic functions (Fig. 5b–d). The successful realization of these basic logic gates also readily enables the construction of a logic half-adder circuit consisting of two NOR gates and two AND gates (Fig. 5e). The half-adder circuit functions well, with a maximum output voltage loss of 2% (Fig. 5f).

Fig. 5: The vdW integration MoS2 logic gates and half-adder.
figure 5

a, Optical microscope image of large-scale vdW-integrated logic gate arrays. b–d, Output characteristics of a NOR gate (b), NAND gate (c) and AND gate (d) fabricated by vdW integration; the insets show schematics of the gates, and all scale bars in insets are 50 μm. The Vin1 and Vin2 represent the first input voltage and the second input voltage in logic gates, respectively. e,f, Optical microscope image (e) and corresponding output characteristics (f) of a monolayer MoS2-based half-adder.

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Conclusions

By adapting a standard contact mask-aligner for the vdW integration process on larger area CVD-grown monolayer MoS2, we successfully demonstrated that the vdW integration process can be adopted for scalable and reliable fabrication of 2D semiconductor electronics at the wafer scale. Importantly, we showed that precise control of the competing adhesion/separation between the PDMS–PMMA and PMMA–substrate interfaces is critical for ensuring reliable and scalable pickup/release processability over a large area. We have shown that a vdW integration strategy could be used to fabricate high-performance monolayer MoS2 transistors and circuits with a high yield and high consistency that is difficult to achieve with a conventional integration strategy. Additionally, such an offset could be significantly optimized through advanced development of industry tools, such as in electro-optical systems, computer-aided control systems, precision mechanics and size-scaling compensation approaches. Such wafer-scale vdW integration can also be employed for multilayer integration to enable 3D integration that is connected through via holes. The demonstration of high-yield wafer-scale vdW integration highlights the fundamental scalability of this approach and marks a critical step towards high-performance 2D electronics. In particular, the implementation of an industry-compatible mask-aligner for scalable vdW integration is critical for the scalable processing of high-performance 2D electronics for future technologies.

Methods

Growth of MoS2 films

The MoS2 films were grown in a three-temperature-zone furnace11. Commercially sourced sulfur (Alfa, 99.9%, 6 g) and MoO3 (Alfa, 99.999%, 60 mg) powders were loaded in two separate inner tubes and then placed in zone I and zone II, respectively. Two-inch sapphire substrates were placed in zone III. Then, the two inner tubes were exposed to an Ar flow (100 sccm) and Ar/O2 flow (75/3 sccm) during the growth. The temperatures for the S, MoO3 and sapphire substrate were 115, 530 and 930 °C, respectively. The pressure in the growth chamber was ~1 torr, and the growth lasted for ~40 min.

Transfer of MoS2 films

First, a layer of BP-212 photoresist was spin-coated on MoS2/sapphire at a speed of 3,000 r.p.m. and then baked at 110 °C for 5 minutes. Second, a layer of PMMA was spin-coated on the sample with the same process. Next, thermal release tape was attached on the sample, and then the sample was immersed in 10% KOH solution for 1 min. The thermal release tape/PMMA/photoresist/MoS2 layer was peeled off using tweezers and moved to the surface of pure water for washing several times before this layer was transferred to the target substrate with a PDMS stamp. The thermal release tape was used to keep the MoS2 film flat, and the PMMA/photoresist/MoS2 layer was released on the substrate at 120 °C. After full release, the sample was washed in acetone for 30 min to remove all polymer.

Device fabrication and measurement

First, Ti/Au (15/15 nm) local gate electrodes were defined on the substrate following standard photolithography, electron-beam evaporation and lift-off processes. Second, a 12 nm Al2O3 dielectric layer or 6 nm HfO2 dielectric layer was deposited using atomic-layer deposition at a processing temperature of 100 °C. For logic circuits, via regions were etched by 5% NaOH solution. Next, MoS2 film was transferred onto the substrate, and then photolithography and vacuum metallization (Ag/Au, 30/20 nm) were used to define the source and drain electrodes on the MoS2 film for the evaporated devices. Ag metal was chosen as the contact since its work function matches well with the MoS2 conduction band, for optimum electron transport. For the vdW integration devices, the metal electrodes were defined onto a sacrificial substrate (285-nm-thick SiO2/Si) following hexamethyldisilazane treatment (80 °C in an oven for 10–20 minutes) before the prefabricated source and drain electrodes were transferred to the MoS2 film by the vdW integration approach. This large-area vdW integration approach can be used to fabricate devices on a 2-inch wafer (or at the wafer scale) with 14,580 FETs in total. After the vacuum metallization process, photolithography or electron-beam lithography was used to define the channel regions, and then a redundant MoS2 film was etched by oxygen plasma. The metal–semiconductor interface is kept clean because the polymer residue of the MoS2 surface is usually very hard and can be removed after the plasma etching process. All device transport measurements were conducted in a Lakeshore vacuum probe station with semiconductor parameter analysers (Keysight 2912A and Agilent B1500). Before the measurement, the devices were annealed at 160 °C for 1 h.