Fig. 4: iSWAP implementation.
a, Detecting region slices for a Z-type bulk detector in the iSWAP circuit, written in terms of CX-SWAP gates, equivalent to the iSWAP gate under single-qubit rotations (Supplementary Information section E1). b, Measured logical error probability for a distance-5 and embedded distance-3 surface codes implemented using the iSWAP circuit and decoder H*. c, Comparative decoder performance. d, Cumulative distribution function (CDF) for the measured Sycamore (pink) and iSWAP (green) inferred two-qubit (2Q) Pauli errors from XEB, with the difference arising from the c-phase. e, Detector error budget from component benchmarks, where CP is the c-phase. f, Energy level diagram for the CZ and iSWAP gates, showing the single- and two-excitation manifolds. Computational states are coloured, and primary leakage pathways are indicated with red arrows. g, Leakage injection experiment with resulting data shown in h. After ten rounds of error correction, \(\left\vert 2\right\rangle\) state leakage is injected on a data qubit, and leakage is measured at each time slice after. h, Measured leakage slicing after injection for the standard CZ implementation with (black) and without (blue) DQLR and for the iSWAP implementation without DQLR (green). The reference experiments without injection are shown as dotted lines.
