Main

Quantum error correction (QEC) enables accurate quantum computation in the presence of uncontrolled physical noise1. The surface code2,3,4 is a preeminent example, capable of suppressing physical errors below a relatively high threshold and providing excellent capabilities for logical computation5,6. These desirable characteristics have inspired extensive experimental work on the surface code7,8, including recently demonstrated below-threshold performance on a superconducting quantum processor9 and transversal logical gates in a neutral atom quantum processor10. So far, all these experiments have been designed around a square grid of statically assigned qubits implementing CNOT/CZ entangling interactions to match the standard circuit implementation. This was assumed to represent the least demanding experimental implementation of the code, as fault-tolerant circuits have traditionally been constructed using static QEC codes.

Recent progress in the theory of time-dynamic QEC, including dynamic codes11 and space-time stabilizers12,13, challenge the traditional static stabilizer approach and unlock new opportunities for the construction of fault-tolerant circuits. The new framework of the space-time detecting region generalizes these approaches, defined by local and connected regions of space-time that report the presence of errors. This framework permits the reinterpretation of QEC circuits as intermeshed detecting regions, featuring overlapping sensitivity such that all physical errors can be appropriately triangulated. It also highlights that maintaining the precise shape of such detecting regions is less crucial than ensuring all circuit locations are covered. Exploiting this freedom opens the door to an expansive equivalence class of circuits for implementing well-understood QEC codes14,15,16,17,18, providing distinct flexibility in their hardware implementation.

In this work, we demonstrate the ability to switch out the circuit implementation of the surface code, achieving error suppression from distance-3 to distance-5 with three time-dynamic circuits that feature qualitatively different demands on the underlying hardware. These circuits are examples representing particularly large departures from previous assumptions about the hardware and gateset necessary to implement the surface code. First, we embed the surface code onto a hexagonal grid, reducing the necessary qubit connectivity from four neighbours to three. Second, we perform a walking circuit in which the qubits are dynamically reassigned between data and measure, frustrating the spread of time-correlated errors. Finally, we perform the surface code using iSWAP gates rather than CNOT/CZ gates, demonstrating that QEC can be performed using entangling interactions previously reserved for Noisy Intermediate-Scale Quantum (NISQ) experiments. We operate all three implementations on Willow processors9, optimized for the standard surface code circuit, permitting direct comparisons of performance but leaving open the possibility of optimizing future hardware around alternative circuits.

The newfound freedom in circuit implementation can be understood naturally using detecting regions, which indicate all locations in a QEC circuit where a non-commuting error would be detected by measurements the region touches. Figure 1a shows a standard distance-5 surface code patch, where we highlight a single detecting region in Fig. 1b. This Z-type detecting region is sensitive to any X or Y error occurring in highlighted locations in the circuit. The region propagates through the circuit in the same way that Pauli terms propagate through Clifford operations, illustrated in Fig. 1c, with more details given in ref. 14. The detecting region persists over two consecutive cycles, first expanding from a single qubit to cover the static code stabilizer immediately after the first measurement gate, which we call the end-cycle state, then contracting to end in a second measurement. Time slices of the detecting region are shown in Fig. 1d; using a tiling of space-time through overlapping detecting regions, we ensure that all relevant circuit locations are checked for errors. Given this general framework, circuit flexibility arises by modifying the gate layers and associated detecting regions while preserving the tiling of space-time.

Fig. 1: Dynamic implementation of QEC.
figure 1

a, A distance-5 surface code on a square lattice. The colours indicate the stabilizer Pauli flavour (red, X; blue, Z). b, Propagation rules for the Z-type detecting region. c, A Z-type detection region evolving through the circuit for the standard implementation, highlighting where Pauli errors that anti-commute will be detected. d, Time slices of the detecting region between gate layers of c. e, End-cycle (after measurement) time slices for four surface code implementations: standard, along with hexagonal, walking and iSWAP, which feature alternating end-cycle states.

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The end-cycle states for the three alternative constructions measured in this work are illustrated in Fig. 1e. Each alternative construction features unique alternating end-cycle states, as opposed to the standard code, which has a static end-cycle state. Such periodic deformation of the detecting region tiling allows the alternative circuit constructions. In this Article, we measure the QEC performance of these three time-dynamic circuits in isolation using a logical memory experiment, proving their ability to reduce the logical error rate as the surface code distance is increased from 3 to 5, while discussing their unique hardware requirements.

Hexagonal lattice surface code

The assumed necessity of a square lattice for the surface code has been a driving influence on superconducting device layouts, with experiments so far implementing four local couplings on each qubit7,8,9,19. This strong device requirement adds substantial design complexity and has limited some architectures from implementing the surface code20,21,22.

Using a time-dynamic circuit featuring an alternative detecting region tiling, a recent proposal provides an embedding of the surface code on a hexagonal grid14. In Fig. 2a, we highlight the key insights of this proposal. The first insight is that the last two-qubit gate layer of each QEC cycle can be altered to match the first layer with the CNOT orientation inverted, using the same qubit–qubit coupling layer twice in each cycle. This results in the expanding detecting region being shifted laterally while preserving the square weight-4 pattern of stabilizers. The second key insight is to use a time-reversed circuit every second cycle, refocusing the detecting region to its starting position during the contraction by an opposite lateral shift. This pattern of two opposing detecting regions is sufficient to tile the space-time bulk of the circuit. We include details on the construction of detecting regions at the spatial boundaries in (Supplementary Information section C1).

Fig. 2: Hexagonal lattice surface code.
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a, Z-type detection region time slices. Each frame shows a gate layer and detecting region after. b, Measured logical error probabilities for a distance-5 and five constituent distance-3 hexagonal lattice surface codes with decoder H*. c, Comparison of decoders: Correlated matching (C) and Harmony (H) (asterisk indicates a reinforcement learning prior). d, Detection probability budget. Solid grey and black lines are measured boundary and bulk detection probabilities, respectively, for d = 5, cycles = 54 and shots = 200,000. Stacked regions indicate component contributions (ordered matching (e)). Detectors are sorted by spatial coordinate in order of increasing probability and are time-ordered within each coordinate. e, Distributions of detection contributions for each error type. CZ, controlled-Z; DD, dynamical decoupling; RO, readout; H, Hadamard; NL, nonlinear (the contribution beyond a linear budget approximation (Supplementary Information section A4)); I, non-DD idle; LR, leakage removal; R, reset. Boxes represent the interquartile range; horizontal lines indicate the median; triangles denote the mean; whiskers extend to 1.5× interquartile range.

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We benchmark the hexagonal implementation using memory experiments run on a superconducting quantum processor. We first prepare the X or Z logical state, apply a variable number of error correction cycles and finally measure the logical qubit in the initialized logical basis. We use the same 72-qubit device as in ref. 9, which features flux-tunable capacitive couplers23,24. We tune the unused couplers to their zero-coupling bias. The distance-5 hexagonal lattice circuit uses 49 computational qubits and 64 couplers, 20% fewer than the 80 couplers used in the standard implementation. Even with fewer physical couplers used, the bulk detecting regions of both standard and hexagonal lattice implementations touch 22 CNOT gates, leading to similar sensitivity to two-qubit gate errors (Supplementary Information section B). We optimize the operating frequencies of the gates taking into account the geometry of the circuit as in ref. 25. In addition, we use the data qubit leakage removal (DQLR) technique developed in ref. 26 to mitigate the impact of leakage on the logical performance.

We run the memory experiment for a distance-5 hexagonal surface code and five tiling distance-3 codes. In Fig. 2b, we report the logical error probability at varying circuit depths, along with the logical error rate per cycle for different decoders (Fig. 2c), ordered from fastest to most accurate. Using the Harmony decoder27 with a noise model prior trained using reinforcement learning28, we measure a distance-5 logical error rate of ϵ5 = 0.270(3)% and a mean distance-3 logical error rate of ϵ3 = 0.580(2)% (averaged over five codes), fit with the same procedure described in ref. 9. From this, we extract an error suppression factor of Λ35,hex = ϵ3/ϵ5 = 2.15(2), indicating the surface code can be operated on a hexagonal lattice with performance matching the standard square lattice implementation (Λ35,standard = 2.14(2))9.

To build confidence in our results, we measure the fidelity of each component of the error correction circuit through independent benchmarking. From these benchmarks and the circuit’s detecting region description, we analytically compute a linear error budget for each region’s detection probability, shown in Fig. 2d and accurate to first order in physical error probabilities (Supplementary Information section A4). We validate this budget by computing the root mean square (RMS) between the analytic prediction and measured value for detection probabilities, finding an RMS of 6.95 × 10−3 for the distance-5 code over 54 cycles (Supplementary Information section C3). In Fig. 2e, we summarize the distribution of different physical error contributions to the detection probabilities. The dominant source of errors are the entangling gate (CZ), the idling error on data qubits during measurement and reset (dynamical decoupling) and readout. Because the boundary detectors use twice-fewer entangling gates, the CZ contribution is halved. Single-qubit gates, leakage removal and reset combined make up only 15% of the detection budget, highlighting the quality of these operations.

Walking surface code

In the standard circuit construction for a QEC code, a static set of data qubits are used to support logical information, and static measure qubits are added to perform the parity checks. The strict distinction between these two categories has a direct consequence in hardware implementations. For example, the data qubits always hold important logical information and therefore are never replaced or reset to their ground state \(\left\vert 0\right\rangle\), allowing them to accumulate non-computational errors. In superconducting circuits, leakage to \(\left\vert 2\right\rangle\) and higher represents one such accumulating error, limiting experimental performance7,29 and requiring hardware intervention26,30,31,32. In cold atom implementations, qubit loss when the atoms escape the trap is another critical example of an accumulating error10,33,34,35. In the framework of detecting regions demonstrated here, the distinction between measure and data qubits is not necessary. It has been proposed that the surface code can be implemented using a circuit where each qubit alternates each cycle between the measure and data roles14,17. These circuits also shift the physical qubit support of the logical qubit and permit movement through space, so we refer to them as walking circuits.

In a walking circuit, each physical qubit experiences a measurement and an opportunity for reset or replacement every two cycles. For superconducting qubits, if a multilevel reset strategy is used at each cycle, the walking circuit presents the advantage of periodically removing leakage from all qubits. For neutral atoms, it relaxes the necessary atom lifetime between opportunities for loss detection and replacement, limiting the errors induced by a loss event and allowing rapid atom replacement with a minimal impact on logical performance.

Walking is permitted by the gate layers and detecting region time slices shown in Fig. 3a. Using this walking circuit, we benchmark the scaling of a logical memory on a 105-qubit superconducting quantum processor9 (a different device than was used for the hexagonal implementation), with logical error probability results shown in Fig. 3b and logical error rate per cycle for different decoders in Fig. 3c. Here, we realize the distance-5 and embedded distance-3 walking circuits without any explicit leakage removal strategy other than multilevel reset (no DQLR). To allow room for walking, the distance-5 circuit utilizes 58 qubits—more than the 49 used in the standard circuit—resulting in a slight overhead in the logical error rate. For a logical memory experiment, we measure distance-5 and average distance-3 logical error rates of ϵ3 = 1.18(3)%, ϵ5 = 0.70(2)%, leading to an error suppression factor Λ35,walk = 1.69(6). The median CZ Pauli error of 3.56 × 10−3 used in the walking circuit is 47% larger than the hexagonal implementation (Supplementary Information section D2), leading to a reduction in Λ35.

Fig. 3: Walking implementation.
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a, Detecting region slices for a Z-type bulk detector in the walking circuit. b, Measured logical error probability for a distance-5 and embedded distance-3 surface codes implemented using the walking circuit and decoder H*. c, Comparison of different decoders. d, Measured average leakage on the A and B data qubit sublattices after each walking circuit gate layer, with leakage data per qubit shown in the upper-right corner. To mitigate an outlier, the highlighted qubit used a single-level reset instead of a multi-level reset. Average leakage for both sublattices over 12 cycles is shown in the lower right. The steady state is reached rapidly, and no rise in leakage over time is visible. e, Comparison of the average detector autocorrelation for three circuits: the standard surface code without DQLR (orange), with DQLR (blue) and the walking circuit without DQLR (green). Long-time correlations in the standard code without DQLR are removed using walking or DQLR. f, Detector error budget from the component benchmarks.

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To benchmark the walking circuit’s leakage dynamics, we measure the leakage population at each time slice of the circuit, separated into the two subgrids of qubits as shown in Fig. 3d. At each moment when a reset is applied to a group of qubits, the leakage population on that group drops by around an order in magnitude, followed by a ramp in population until they are reset again two cycles later. The staggered multilevel reset applications limit leakage population build-up over many cycles, preventing a rising contribution to the overall logical performance as the code continues.

Leakage also causes time-correlated errors that are not properly handled by the decoder. We directly probe these correlations by measuring the detector autocorrelation in Fig. 3e, which is the average covariance of the detecting events separated by n cycles. While two-round correlations are expected from time-like Pauli errors (for example, readout or reset errors), this measurement reveals longer time correlations induced by non-Pauli errors. Without leakage removal in the standard code, we measure a long correlation tail lasting nearly 50 cycles, while the walking circuit and the standard code with leakage removal substantially reduce these long-time correlations.

In addition to these leakage measurements, we apply the same detector budgeting techniques introduced in the previous section to reveal the contributions of each physical error mechanism on detection probabilities in the circuit (Fig. 3f). Our Pauli model produces detections that have a weaker correlation with experiment (RMS of 2.01 × 10−2; Supplementary Information section D3)) than the hexagonal implementation, indicating that some error mechanisms are not fully captured by the Pauli model, but reveals the same dominant contributions as the hexagonal implementation. The CZ gate contribution is larger, as expected due to reduced gate performance. Even with the reduction in logical performance and Λ35, our results demonstrate that a walking surface code can suppress errors as distance increases with a built-in leakage removal, paving the way for new architectures that can use this property to their advantage.

iSWAP surface code

The third implementation explored in this work uses the iSWAP family of gates for the entangling layers instead of the standard CNOT/CZ family. It was previously unclear how to implement QEC using the iSWAP gate, as it distorts the stabilizers, preventing them from returning to their initial static code state. However, using the dynamic circuit technique of time-reversing every second cycle, we can find complementary distortions of the stabilizers that permit the iSWAP gate to preserve the structure of the surface code. In Fig. 4a, we show the expansion and contraction of a single detecting region. The end cycles form a distorted arrowhead shape instead of the usual square. Nonetheless, the arrowhead pattern can be clearly identified as a two-colourable checkerboard of weight-4 X and Z stabilizers, sufficient for QEC of the surface code.

Fig. 4: iSWAP implementation.
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a, Detecting region slices for a Z-type bulk detector in the iSWAP circuit, written in terms of CX-SWAP gates, equivalent to the iSWAP gate under single-qubit rotations (Supplementary Information section E1). b, Measured logical error probability for a distance-5 and embedded distance-3 surface codes implemented using the iSWAP circuit and decoder H*. c, Comparative decoder performance. d, Cumulative distribution function (CDF) for the measured Sycamore (pink) and iSWAP (green) inferred two-qubit (2Q) Pauli errors from XEB, with the difference arising from the c-phase. e, Detector error budget from component benchmarks, where CP is the c-phase. f, Energy level diagram for the CZ and iSWAP gates, showing the single- and two-excitation manifolds. Computational states are coloured, and primary leakage pathways are indicated with red arrows. g, Leakage injection experiment with resulting data shown in h. After ten rounds of error correction, \(\left\vert 2\right\rangle\) state leakage is injected on a data qubit, and leakage is measured at each time slice after. h, Measured leakage slicing after injection for the standard CZ implementation with (black) and without (blue) DQLR and for the iSWAP implementation without DQLR (green). The reference experiments without injection are shown as dotted lines.

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In Fig. 4b,c, we benchmark the logical error rate of a distance-5 and embedded distance-3 iSWAP implementation of surface codes on our 72-qubit device (the distance-5 circuit uses 57 qubits). Using decoder H*, we measure logical error rates of ϵ5 = 0.650(7)% and ϵ3 = 1.015(6)% averaged over the five distance-3 codes, here again without using DQLR (relying on multilevel reset as the only active source of leakage removal). We extract the error suppression factor Λ35,iSWAP = 1.56(2), demonstrating the viability of a surface code implemented with iSWAP gates.

In previous experiments, the so-called Sycamore gate using a short, on-resonance \(\left\vert 01\right\rangle \!-\!\left\vert 10\right\rangle\) interaction has been used as an entangling resource to realize beyond-classical circuits36,37. The Sycamore gate can be decomposed as an iSWAP gate and a controlled-phase gate, with arbitrary angle ϕ (Supplementary Information section E2). While this controlled phase is not a problem for NISQ experiments38, it adds a Pauli error per gate of ϕ2/16 for stabilizer codes that require a strict Clifford gate, as confirmed by coherent simulations. In this work, we choose an iSWAP gate length balancing coherent error from the c-phase and incoherent error, arriving at a longer gate of order 60 ns, roughly twice the CZ length. This additional c-phase error channel can be reduced by tailoring the hardware to the iSWAP, for example by increasing the anharmonicity or using a different gate architecture39. For this gate length, we measure an average c-phase of ϕ = 146 mrad, yielding a Pauli error contribution to the gate of 1.33 × 10−3, as shown in Fig. 4d, for a median inferred iSWAP Pauli error of 4.28 × 10−3 (Supplementary Information section E3), 76% larger than the CZ gates used in the hexagonal implementation. This c-phase error accounts for roughly 19% of the detection probability in the bulk, as shown in Fig. 4e. Although our present device was optimized to realize CZ gates, the iSWAP c-phase error could be suppressed by increasing the anharmonicity in future designs.

Despite the lower gate fidelity on current hardware, one appeal of using iSWAP instead of CZ is the leakage generation and transport. As shown in Fig. 4f, the iSWAP’s on-resonance \(\left\vert 10\right\rangle \!-\!\left\vert 01\right\rangle\) interaction is within the computational subspace and, as a result, does not directly populate non-computational states, minimizing leakage generation. When a higher excited state such as \(\left\vert 2\right\rangle\) is present, it will transport to other qubits through the resonant \(\left\vert 21\right\rangle \!-\!\left\vert 12\right\rangle\) interaction, and this transport can aid in leakage removal by spreading leakage from data qubits to measure qubits where a multilevel reset gate is performed each cycle. This behaviour is in contrast to the CZ gate, which implements an on-resonance \(\left\vert 20\right\rangle \!-\!\left\vert 11\right\rangle\) interaction with a precise timing calibrated to remove population from the \(\left\vert 2\right\rangle\) state. Small errors in CZ calibration can thus generate leakage outside the computational space.

We probe the effect of leakage during memory experiments by measuring the population of excited states following the injection of a \(\left\vert 2\right\rangle\) state on the centre-most bulk data qubit after ten cycles, as shown in Fig. 4g, here using the distance-5 code. We repeat this experiment for three surface code implementations: the standard CZ implementation with and without DQLR, and the iSWAP implementation (which does not use DQLR), with results shown in in Fig. 4h. In a reference experiment where no leakage is injected (dotted lines), the standard surface code without DQLR reaches a steady state with oscillating average leakage between 1.1% and 1.4% per qubit due to the large leakage generation of the CZ gates. With DQLR, the average leaked population is considerably reduced as expected, oscillting between 0.05% and 0.3%. With the iSWAP implementation, the average leakage population reaches an oscillating steady state between 0.1% and 0.45%, limiting leakage well below the standard implementation without DQLR, indicating the superior leakage properties of the iSWAP gate compared with the CZ gate. Among all three, the standard CZ code with DQLR achieves the best leakage performance.

When the \(\left\vert 2\right\rangle\) state is injected after a reset moment, all three implementations spike in their leaked population. The standard implementation without DQLR eliminates the extra leaked population within ten cycles, whereas the DQLR version eliminates the leaked state within two cycles and the iSWAP in four cycles. This demonstrates that the iSWAP implementation can mitigate leakage well without explicit leakage removal, and adding DQLR to the iSWAP implementation could further improve its leakage characteristics.

Scaling and outlook

To compare surface code implementations on current hardware, in Fig. 5a we show contributions of each error component to the inverse scaling factor, 1/Λ35, which can be expanded as a linear sum in physical error rates at first order (Supplementary Information section B). The total cycle times of the implementations are similar (hexagonal: 1,086 ns, walking: 1,028 ns, iSWAP: 1,064 ns), enabling direct comparison. These simulations go beyond the Pauli models used to construct the detector error budgets by including effects such as leakage and crosstalk. For all codes, these leakage and crosstalk contributions are still small relative to the two-qubit gates, dynamical decoupling and readout error. The c-phase contribution for the iSWAP code is substantial, accounting for 16% of the budget, and causes the iSWAP code’s simulated 1/Λ35 to be larger than the other three implementations.

Fig. 5: Lambda budgeting and scaling.
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a, 1/Λ35 error budgets for the hexagonal, walking and iSWAP implementations, compared with the standard implementation from ref. 9. The relative percentages of the dominant categories are given. The plot compares experimental data (Exp., solid line) with simulation (Sim., dashed line), with coloured bars indicating the relative percentages of dominant error sources: 2Q, DD, RO, single-qubit gates (1Q), crosstalk (Xtalk), leakage, reset, heating and CP. b, Simulated logical error rate versus distance for hardware tailored to the hexagonal circuit (three couplers per qubit) compared with a standard square grid layout with the same TLS landscape. Open squares (standard code) and hexagons (hex code) are error rates averaged over multiple simulations (circles).

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For the hexagonal implementation, while the performance we measure already matches state of the art, tailoring the device to a honeycomb or brickwall lattice will reduce the number of connections needed from 2 to 1.5 per qubit (taking into account that qubits share connections). In principle, it will also reduce the number of potential error channels by reducing the complexity of the device. From a frequency optimization perspective, the lower connectivity reduces the number of variables, simplifying the optimization step. In Fig. 5b, we simulate the potential gain of tailoring the hardware to a hexagonal lattice by accounting for realistic device inhomogeneities in hardware parameters as well as two-level system (TLS) density with a frequency optimization step25 (Supplementary Information section G). From these simulations, we predict that simplifying the hardware by removing one coupler per qubit can lead to a 15% improvement of the scaling factor Λ. Such an increase in Λ compounds favourably with a reduction in number of couplers needed, simplifying the design and number of control lines.

With these data, we have demonstrated state-of-the-art error suppression from distance-3 to distance-5 for the hexagonal, walking and iSWAP surface code implementations. This proves that dynamic circuits are a viable approach to fault tolerance, while also unlocking the ability to tailor the error correction circuit to hardware, presenting new opportunities for coupler design, multiplexing and leakage removal intrinsic to the operation of QEC itself. In addition, our budgeting and leakage results offer direct insight into how dynamic circuits reveal new trade-offs in realizing QEC. We envision that other unexplored avenues for dynamic circuits may present further benefits, and our experiments solidify the prospects for the co-design of QEC and hardware as the state of the art for QEC at scale.