Extended Data Fig. 7: The result of digital computation by the 2D RV32 processor.
From: A RISC-V 32-bit microprocessor based on two-dimensional semiconductors
In the first instruction, an operand stored in the register file, “1946” (the year ENIAC was manufactured), and another operand in the instruction as the immediate number, “25”, are added together. On the first clock cycle of this instruction, the valid 32-bit PC is sent to the ibus with the pc_valid flag. The instruction is then sent to RV32-WUJI in the next clock cycle with the inst_valid flag. After several clock cycles for decoding, the counter starts counting while the computation begins: First, the lowest bits of “1946” (“0”) and “25” (“1”) are entered separately into the ALU as rs1 and imm, whose names represent the data from the 1st source register and the immediate numbers. After the addition between the lowest bits is finished, the result bit is written back to the register file as rd, representing the destination register, and the carry is stored in the ALU. Then the second lowest bits are entered and added in the next clock cycle, while the carry stored in the ALU in the last clock cycle is included in the addition this time. The calculation continues until the counter reaches 32 and all 32-bit calculations are complete. A similar calculation is performed in the second instruction, except that both input operands, “1971” and “53”, are from the register file. The final result is 2024, which is 1971 plus 53.
