Fig. 3: Logical randomized benchmarking.
From: Scaling and logic in the colour code on a superconducting quantum processor
a, Logical-qubit-level reference (Ref.; green) and interleaved randomized benchmarking (IRB; blue) circuit diagrams, consisting of error correction cycles (QEC), randomly selected Clifford gates (C1, …, Cm), a Clifford recovery gate C−1 and a Z basis measurement (MZ). b–d, Simplified circuit diagrams for a tile of the colour code indicating measurements included in an X-stabilizer error-detecting region spanning across two consecutive cycles without logical gate (b), and how it changes on the application of a logical Hadamard gate H (c), or a logical phase gate S (d) between two error correction cycles, see text for details. The green, blue and purple highlighted sections correspond to regions in which the detecting region is sensitive to Z, X and both X and Z errors, respectively. A CNOT gate symbol spanning three qubit wires indicates three consecutive CNOTs between the auxiliary qubit and its neighbouring data qubits. e, Measured fidelity (symbols) and exponential fits (solid lines) for the interleaved (blue) and reference (green) sequences compared with the number of logical Clifford gates m. The data are decoded using the neural-network decoder. Error bars represent the standard deviation of fidelity over 25 random Clifford sequences, each repeated 20,000 times.
