Fig. 4

(a) Voltage across diodes and capacitors in Normal state (b) Voltage across diodes and capacitors in reconfiguration state (c) Switching flow graph of proposed fault-tolerant converter in normal mode (d) Switching flow graph of proposed fault-tolerant converter in reconfiguration mode (e) Root locus (f) Bode plot (g) Changes in voltage gain for various value of duty cycle and parasitic resistance (h) Losses in the power components.