Introduction

The growth of solar power exceeded that of all other power generation technologies in 2023. Solar photovoltaic accounted for two-thirds of the new renewable power capacity built last year, with a 24% growth rate in energy generation, the highest of all power-producing technologies. Solar power sources occupy an important role in DC microgrid architecture. In the DC microgrid structure, multiple power converters are used, and they are more vulnerable to variation in the transient condition1. For flexible DC microgrid operation, a multiport dc-dc converter is proposed for controlling the dc link voltage2. A resilient control scheme in a DC microgrid is essential when deployed in difficult terrain3. A robust fault-tolerant series resonant converter is designed for DC microgrids to address the fault in semiconductor switches4. This deliberately shows that seamless control and resilience are required in DC microgrid structures especially, in the power conditioning unit. The researchers are motivated to pave the ground for developing a reliable energy harvesting interface for solar panels and other renewable energy sources5.

Recently, many topologies have been designed and presented for renewable power applications in literature1,2,6,7. On the other hand, the study of fault-tolerant power converter structures has received very little attention. The lifetime of PV/wind turbines is about 20 years, whereas the reliable lifetime of the power converters available in the market is less comparatively. Consequently, the power interfacing unit needs to be replaced twice in the entire reliable operating time of the hybrid renewable energy system. Hence, the most reliable topology for a hybrid renewable energy system is required. The demand for power converters for renewable energy generation has increased rapidly in the past years8.

In the design phase of power converters, it is essential to incorporate the fault-tolerant technique for the most critical application9. About failure analysis in literature, it is inferred that the second most common component prone to failure is PCB (26%) and switch (21%) after the capacitor10. The reliability of the converter is improved by adding redundant components to the converter11,12,13. The failure of an active semiconductor switch will result in catastrophic and irretrievable entire system failure 14. The chief fault occurring component in the power converter is the capacitor due to its charging cycle and degradation of dielectric material. The fault-tolerant structures reported in the literature address the failure of switches rather than the capacitors11,15,16. In all these topologies11,15,16, switch fault is diagnosed, and remedial action is proposed. However, the fault in the capacitors (especially the output capacitor), whose voltage stress is mostly equal to the output voltage of the converter, is not monitored and considered.

A suitable topology will be suggested and presented in the proposal to meet the efficient DC microgrid system requirements. Mostly, in literature, hardware redundancy is proposed for the fault remedial action and validated as an effective way to enhance the reliability of the converter. In17, the fault-tolerant reliable structure is achieved by cascading several modules of quasi-z converters. If a fault occurs in the switch of the converter, the defected module is isolated from the cascaded converters and continues the operation with the help of relays. This fault-tolerant structure has multiple redundant components which increases the initial investment and cooling cost of the converter.

In18, a reconfigurable boost/buck-boost converter is proposed with 1-degree redundancy, i.e., the switch fault is diagnosed and rectified. In this topology, the boost configuration is restructured to the buck-boost configuration when the switch fault occurs. Still, the fault-tolerant topologies with the reconfiguration technique are not yet fully explored. According to the present context of research in the proposed area, reconfigured topology with 2-degree redundancy (switch and capacitor) is not explored in the literature, which will be taken as the objective to offer a novel topology with the 2-degree redundancy along with the reconfiguration technique. In addition to this, a power management strategy will be suggested to provide an interactive operative platform for renewable power sources and to coordinate their work according to the requirements of the microgrid6,7. Energy management is mandatory in microgrids because it provides a reliable operation even during disturbances and contingency19,20. Presently, this research is appreciated since it allows for an uninterruptible system with smooth running by prioritizing the sources.

In India, 2.4 percent of households still do not have access to electricity. These rural dwellings will benefit from a renewable DC system. Villages in rugged terrains, such as deserts, islands, mountains, and so on, require a reliable power supply system because replacing failed components is difficult and time-consuming. As a result, it is recommended that a reliable system be designed, with the design of a power conditioning unit being essential because it is more prone to failure. Faults in power components can be controlled using a suitable fault-tolerant technique if the reliability analysis of the power converter is well investigated21.

Table 1 presents the literature survey on the type of converter considered for fault-tolerant study with the component whose fault is addressed. The survey on the incorporation of reconfiguration features with the uninterrupted operation is also considered and presented. From this study, it is observed that most switch faults are considered for analysis. In literature, fault diagnosis and identification are much explored compared to the derivation of fault-tolerant reconfigurable topology. It is also noted that there is a lot of scope in carrying out the research in proposing reconfigurable fault-tolerant topology without altering the key performance of the converter.

Table 1 Status on reconfiguration and fault-tolerance in DC-DC converter in the literature.
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Fault tolerance with single-degree redundancy is primarily addressed and tested in the literature. According to the present research context in the proposed area, reconfigured topology with 2-degree redundancy is not explored in the literature, which will be the primary objective. The novel parts in the proposed configuration are the derivation of high gain topology and the design of the fault-tolerant structure with restructuring in case of failures without altering the voltage gain. The additional feature of the topology is the reduction in input current ripple which is required for the system powered by renewable energy sources22.

The main contributions of this work are summarized as follows: 1. Novel reconfigurable fault-tolerant topology is proposed with salient features. 2. Reliability evaluation of the proposed topology is performed, and it is compared with a conventional quadratic boost converter. 3. The proposed RFTQB topology is compared with the existing topology in the literature to highlight its significant features. 4. Testing of normal operating and reconfiguration mode of proposed topology with 1-kW prototype. 5. Experimental setup is validated by conducting with programmable dc supply and solar PV modules.

This article is organized as follows: circuit configuration of a restructured quadratic boost converter with fault-tolerant capability is presented in Sect.  2. In Sect.  3, the steady-state analysis of restructured topology in normal and reconfigured states is discussed with appropriate waveforms and diagrams. In the same section, efficiency, dynamic and sensitivity analysis with non-ideal voltage gain is performed. The proposed topology is compared with a conventional quadratic boost converter and its superiority is highlighted. The reliability study of the proposed converter in normal and reconfigured state is performed and compared in Sect. 4. In Sect.  5, a comparative analysis is performed with similar fault-tolerant topologies reported in the literature. The simulation and hardware results are obtained to validate the theoretical study of the suggested topology with the results depicted in Sects. 6 and 7 respectively. Finally, the results are concluded in Sect. 8. The nomenclature for this study is provided in the supplementary file.

Proposed reconfigured fault-tolerant quadratic boost converter (RFTQB)

Figure 1 illustrates the average price of solar panels per watt and global solar PV module production over time (2010–2020). It depicts that the solar module price has declined to 90%, and the solar deployment has risen to 400%. The researchers are motivated to pave the ground for developing a reliable energy harvesting interface for solar panels and other renewable energy sources. Figure 1b depicts the percentage of failure in the components of the power converters. From this figure, it is observed that the capacitor and switch occupy more than 50% of the failure in the components of the power converter. Taking this into consideration, 2-degree redundancy is proposed for quadratic boost converter with additional features.

Fig. 1
figure 1

(a) Cost of solar panel and its production (b) Failures in power converter.

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Figure 2 presents the overview of the proposed fault-tolerant structure configuration. Figure 2a depicts the derivation of the proposed structure by modifying the conventional quadratic boost converter. In this proposed configuration, inductors (L1 and L2) are transferred to the bottom rail of the circuit. Similarly, the input side diode D1 is shifted between the emitter of the IGBT and the inductor L1. Diode D2 is shifted between the negative polarity of the input capacitor, C and the inductor L1. Finally, the output diode is moved between the negative polarity of the output capacitor, Co and the inductor L2. By transferring these components, a novel fault-tolerant converter is designed with 2-level of redundancy. This topology is more appropriate for standalone applications.

Fig. 2
figure 2

(a) Derivation of the proposed structure (b) Reconfigured Fault-tolerant Quadratic boost converter (RFTQB) (c) RFTQB converter with faulted components considered for analysis (d) RFTQB converter in normal state (e) RFTQB converter in reconfiguration state.

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Figure 2b depicts the circuit configuration of the reconfigured fault-tolerant quadratic boost converter (RFTQB). Figure 2c highlights the faulted components which are addressed in the proposed converter. The circuit configuration of the normal and reconfiguration state of the RFTQB converter is presented in (Fig. 2d,e).

Figure 2d depicts the conventional quadratic boost converter with the components switched to the bottom rail. The RFTQB topology is derived from the conventional quadratic boost converter. Diodes (D1, D2 and Do) and Inductors (L1 and L2) are shifted to the bottom rail as shown in (Fig. 2e). Additional switch, SWR, input capacitor, CR and output capacitor, CoR are added to operate the topology in a reconfiguration state. As a result, the circuit configuration design is converted to floating output. Such a type of circuit is more suitable for applications such as standalone applications with battery storage. Three fuses are added in series with the switch and capacitors to isolate the components from fault occurrence. Switch, SWR is added just parallel to the main switch, SW and it will be active only when the main switch is subjected to a fault. In literature12, switch fault is addressed by adding redundancy to the circuit with the additional switch.

Compared with the converter proposed in17, the proposed topology addresses the failure of the individual components with the redundant component rather than the redundant circuit/module. In17, sensors and relays are used for designing the fault-tolerant structure. The output voltage of the cascaded quasi-z source converter17 is monitored through the sensor. When the voltage is decreased, the relay isolates the defective module and increases the duty cycle of the healthy converter.

In the case of the proposed topology, an extra three components (2 capacitors and 1 switch) which are more prone to failures are added as redundant to make the converter with fault tolerance features. Apart from the fault-tolerant capability, the proposed topology has additional features in reconfiguration such as a reduction in the voltage stress of the input and output capacitors. This is validated in the following section with steady-state analysis.

Normal mode

In this mode, the topology operates as the traditional quadratic boost converter. The voltage stress across the diodes, switch and capacitor is similar to a quadratic boost converter.

Reconfiguration mode

This mode is active only when there is a fault occurrence in the switch and capacitor. The working of the topology with the fault in each component is discussed in Fig. 3. Redundant components for input capacitor (CR), Output capacitor (CoR) and switch (SWR) are conducted in the circuit. The redundant components will come into the picture after the fault occurrence. These three faults with their circuit configuration are depicted in (Fig. 3a–c).

Fig. 3
figure 3

Circuit configuration (a) Input capacitor fails (b) Output capacitor fails (c) Switch fails.

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It is observed that in both the working modes, the voltage stress across the switch is equal to the output voltage. The stress across the switch can be alleviated by a adding voltage multiplier (diode-capacitor) cell after the switch and before the load. This will result in an increase in the gain of the topology. This configuration mainly concentrates on the reduction in the stress of the capacitor. This voltage stress reduction is validated in the next section by performing a steady-state analysis.

Steady-state analysis of RFTQB converter

To validate the performance of the RFTQB converter, the steady-state analysis is performed by applying the volt-second balance law for the normal and reconfiguration modes. The voltage across the inductors (L1 and L2) in both modes is observed and tabulated in (Table 2). The modes of operations with the current flow in the circuit are presented. After applying the volt-sec balance principle, a general expression is obtained.

Table 2 Modes of operation of RFTQB converter in normal and reconfiguration state.
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Derivation of output voltage

By applying voltage-second balance principle for normal mode of operation with ON and OFF switching period yields,

The voltage across the input capacitor as

$$V_{C} = \frac{{V_{dc} }}{1 - D}$$
(1)

The voltage across the output capacitor is equal to the output voltage.

Finally, the voltage conversion ratio of the proposed topology in the normal mode of operation is computed as

$$V_{O} = \frac{{V_{dc} }}{{(1 - D)^{2} }}$$
(2)

Voltage stress across the redundant capacitors

Similarly, the voltage-second balance principle is applied for reconfiguration mode of operation with ON and OFF switching period and the voltage across the redundant input capacitor is

$$V_{CR} = \frac{{V_{dc} D}}{1 - D}$$
(3)

The voltage across the redundant output capacitor is

$$V_{COR} = V_{O} - V_{dc} = \frac{{V_{dc} D(2 - D)}}{{(1 - D)^{2} }}$$
(4)

The unaltered voltage gain of the proposed reconfigurable fault-tolerant quadratic boost converter in reconfiguration mode is computed and it is similar to (2).

It is observed that the voltage gain of the converter is retained in all the modes of operation with the occurrence of fault. In Fig. 2a–c it is also noted that the voltage conversion ratio of the converter with the fault in input, output and switch fault remains the same as (2). In (2), Vdc is the voltage from the solar panel. Similarly, the voltage stress across the switch and diodes (D1, D2 and Do) remain the same and it is presented in (Table 2). The voltage across diodes and capacitors in the normal and reconfiguration mode is depicted in Fig. 4. The voltage stress across the capacitors in the configuration varies with the occurrence of fault.

Fig. 4
figure 4

(a) Voltage across diodes and capacitors in Normal state (b) Voltage across diodes and capacitors in reconfiguration state (c) Switching flow graph of proposed fault-tolerant converter in normal mode (d) Switching flow graph of proposed fault-tolerant converter in reconfiguration mode (e) Root locus (f) Bode plot (g) Changes in voltage gain for various value of duty cycle and parasitic resistance (h) Losses in the power components.

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Design of passive components

The input current ripple is given as

$$\Delta {i}_{L1}=\frac{{V}_{dc}}{2{L}_{1}}D{T}_{S}$$
(5)

\({I}_{dc}>\Delta {i}_{L1}\) for continuous conduction mode

$$\frac{{I}_{O}}{{(1-D)}^{2}}=\frac{{I}_{O}{R}_{O}{(1-D)}^{2}}{2{L}_{1}}D{T}_{S}$$
(6)

Simplifying the (6) yields

$${L}_{1}=\frac{{R}_{O}{(1-D)}^{4}D}{2{f}_{S}}$$
(7)

Similarly, the design expression for the second inductor L2 is obtained as

$${L}_{2}=\frac{{R}_{O}{(1-D)}^{2}D}{2{f}_{S}}$$
(8)

The design value of capacitor C and Co is obtained as

$$C=\frac{{I}_{O}D}{(1-D){f}_{S}\Delta {V}_{C}}$$
(9)
$${C}_{O}=\frac{{I}_{O}D}{{f}_{S}\Delta {V}_{CO}}$$
(10)

Voltage/Current stress on semiconductors

He current stress on the diodes (D1, D2 and DO) is acquired as

$${I}_{D1}=\frac{{I}_{O}\sqrt{D}}{{(1-D)}^{2}}$$
(11)
$${I}_{D2}=\frac{{I}_{O}}{{(1-D)}^{3/2}}$$
(12)
$${I}_{DO}=\frac{{I}_{O}}{\sqrt{1-D}}$$
(13)

The current stress on switch is obtained as

$${I}_{SW}=\frac{{I}_{O}(2-D)\sqrt{D}}{{(1-D)}^{2}}$$
(14)

The voltage stress across the semiconductors is derived as

$${V}_{D1}=\frac{{V}_{dc}D}{{(1-D)}^{2}}$$
(15)
$${V}_{D2}=\frac{{V}_{dc}}{(1-D)}$$
(16)
$${V}_{DO}=\frac{{V}_{dc}}{{(1-D)}^{2}}$$
(17)
$${V}_{SW}=\frac{{V}_{dc}}{{(1-D)}^{2}}$$
(18)

Efficiency analysis

The power loss in the passive components is obtained as

$${{\varvec{P}}}_{{\varvec{L}}}={{{\varvec{I}}}_{{\varvec{d}}{\varvec{c}}}}^{2}\left[{{\varvec{G}}}_{{\varvec{V}}}{{\varvec{R}}}_{{\varvec{L}}1}+{{\varvec{R}}}_{{\varvec{L}}2}\right]$$
(19)
$${{\varvec{P}}}_{{\varvec{c}}}=\frac{{{{\varvec{I}}}_{{\varvec{O}}}}^{2}{\varvec{D}}}{(1-{\varvec{D}})}\left[{{\varvec{G}}}_{{\varvec{V}}}{{\varvec{R}}}_{{\varvec{C}}}+{{\varvec{R}}}_{{\varvec{C}}{\varvec{O}}}\right]$$
(20)

where GV is the voltage gain of the converter and it is equal to 1/(1−D)2. RL and RC are the internal resistances of the passive components.

The power loss in the semiconductor devices is computed as

$${{\varvec{P}}}_{{\varvec{D}}}={{\varvec{I}}}_{{\varvec{d}}{\varvec{c}}}(1+{\left(1-{\varvec{D}}\right)}^{2}){{\varvec{V}}}_{{\varvec{F}}}+\frac{{{{\varvec{I}}}_{{\varvec{d}}{\varvec{c}}}}^{2}(1+{\left(1-{\varvec{D}}\right)}^{3})}{{(1-{\varvec{D}})}^{2}}{{\varvec{R}}}_{{\varvec{F}}}$$
(21)

where VF and RF are forward voltage drop and internal resistance of diode.

$${{\varvec{P}}}_{{\varvec{S}}{\varvec{W}}}={{\varvec{I}}}_{{\varvec{d}}{\varvec{c}}}\left(2-{\varvec{D}}\right)\left[{{\varvec{I}}}_{{\varvec{d}}{\varvec{c}}}\left(2-{\varvec{D}}\right){{\varvec{R}}}_{{\varvec{C}}{\varvec{E}}}+{{\varvec{f}}}_{{\varvec{s}}{\varvec{w}}}{{\varvec{C}}}_{{\varvec{O}}{\varvec{e}}{\varvec{s}}}{{{\varvec{V}}}_{{\varvec{O}}}}^{2}\right]$$
(22)

where RCE is the on-state resistance of IGBT switch. Coes is the IGBT output capacitance.

The efficiency of the proposed converter is determined by

$${\varvec{\eta}}=\boldsymbol{ }\frac{{{\varvec{P}}}_{{\varvec{O}}}+{{\varvec{P}}}_{{\varvec{L}}}+{{\varvec{P}}}_{{\varvec{C}}}+{{\varvec{P}}}_{{\varvec{D}}}+{{\varvec{P}}}_{{\varvec{S}}{\varvec{W}}}}{{{\varvec{P}}}_{{\varvec{O}}}}$$
(23)

By considering Po = 200 W, Vdc = 50 V, Vo = 200 V, Ro = 200 Ω, RF = 0.083 Ω, VF = 2,5 V, RCE = 10 mΩ, RL = 160 mΩ, RC = 290 mΩ and COES = 0.4 nF. The efficiency of the fault-tolerant power converter is computed, and its theoretical efficiency is 90%. The loss distribution is presented in (Fig. 4g).

Dynamic analysis

The dynamic study of the proposed converter is performed using the switching flow graph (SFG) technique. Figure 4c,d present the SFG of the fault-tolerant converter in normal and reconfiguration modes respectively.

$$\frac{{\user2{V}_{\user2{O}} \left( \user2{s} \right)}}{{\user2{V}_{{\user2{dc}}} \left( \user2{s} \right)}}\left( {\user2{normal}} \right) = \frac{{{{\left( {1 - \user2{D}} \right)^{2} } \mathord{\left/ {\vphantom {{\left( {1 - \user2{D}} \right)^{2} } {\user2{L}_{2} \user2{CC}_{\user2{O}} }}} \right. \kern-\nulldelimiterspace} {\user2{L}_{2} \user2{CC}_{\user2{O}} }}}}{{\user2{S}^{4} + \frac{{\user2{S}^{3} }}{{\user2{R}_{\user2{O}} \user2{C}_{\user2{O}} }} + \user2{S}^{2} \left[ {\frac{1}{{\user2{L}_{2} \user2{C}}} + \frac{{\left( {1 - \user2{D}} \right)^{2} }}{{\user2{L}_{2} \user2{C}_{\user2{O}} }} + \frac{{\left( {1 - \user2{D}} \right)^{2} }}{{\user2{L}_{1} \user2{C}}}} \right] + \frac{\user2{S}}{{\user2{R}_{\user2{O}} \user2{CC}_{\user2{O}} }}\left[ {\frac{1}{{\user2{L}_{2} }} + \frac{{\left( {1 - \user2{D}} \right)^{2} }}{{\user2{L}_{1} }}} \right] + \frac{{\left( {1 - \user2{D}} \right)^{4} }}{{\user2{L}_{1} \user2{L}_{2} \user2{CC}_{\user2{O}} }}}}$$
(24)
$$\frac{{\user2{V}_{\user2{O}} \left( \user2{s} \right)}}{{\user2{V}_{{\user2{dc}}} \left( \user2{s} \right)}}\left( {\user2{reconf}} \right) = \frac{{{{\left( {1 - \user2{D}} \right)^{2} } \mathord{\left/ {\vphantom {{\left( {1 - \user2{D}} \right)^{2} } {\user2{L}_{2} \user2{C}_{\user2{R}} \user2{C}_{{\user2{OR}}} }}} \right. \kern-\nulldelimiterspace} {\user2{L}_{2} \user2{C}_{\user2{R}} \user2{C}_{{\user2{OR}}} }}}}{{\user2{S}^{4} + \frac{{\user2{S}^{3} }}{{\user2{R}_{\user2{O}} \user2{C}_{{\user2{OR}}} }} + \user2{S}^{2} \left[ {\frac{1}{{\user2{L}_{2} \user2{C}_{\user2{R}} }} + \frac{{\left( {1 - \user2{D}} \right)^{2} }}{{\user2{L}_{2} \user2{C}_{{\user2{OR}}} }} + \frac{{\left( {1 - \user2{D}} \right)^{2} }}{{\user2{L}_{1} \user2{C}_{\user2{R}} }}} \right] + \frac{\user2{S}}{{\user2{R}_{\user2{O}} \user2{C}_{\user2{R}} \user2{C}_{{\user2{OR}}} }}\left[ {\frac{1}{{\user2{L}_{2} }} + \frac{{\left( {1 - \user2{D}} \right)^{2} }}{{\user2{L}_{1} }}} \right] + \frac{{\left( {1 - \user2{D}} \right)^{4} }}{{\user2{L}_{1} \user2{L}_{2} \user2{C}_{\user2{R}} \user2{C}_{{\user2{OR}}} }}}}$$
(25)

Figure 4e depicts the root locus of the proposed converter. The plot displays four loci, totaling four poles. All the poles lie on the imaginary axis. Two loci are moving towards the left of the plane, and the other two are moving towards the right of the plane. The plot analysis reveals that the converter is marginally stable.

Figure 4f exhibits the Bode responses of the proposed converter. It is a type 0 system and has four poles. The gain reaches 0 dB, and the phase reaches 180 degrees at various frequencies. Due to the system being classified as type 0, the magnitude plot remains constant at low frequencies, whereas the phase tends towards 0 degrees at these frequencies.

Derivation of non-ideal voltage gain

The overall loss of fault-tolerant converter is presented as

$${P}_{LS}={P}_{L}+{P}_{C}+{P}_{D}+{P}_{SW}$$
(26)
$$P_{{LS}} = P_{O} \left[ \begin{gathered} \frac{{R_{{L1}} }}{{\left( {1 - D} \right)^{4} R_{O} }} + \frac{{R_{{L2}} }}{{\left( {1 - D} \right)^{2} R_{O} }} + \frac{{R_{C} D}}{{\left( {1 - D} \right)^{3} R_{O} }} + \frac{{R_{{CO}} D}}{{\left( {1 - D} \right)R_{O} }} + \hfill \\ \frac{{V_{F} \left( {1 + \left( {1 - D} \right)^{2} } \right)}}{{\left( {1 - D} \right)^{2} V_{O} }} + \frac{{R_{F} \left( {1 + \left( {1 - D} \right)^{3} } \right)}}{{\left( {1 - D} \right)^{4} R_{O} }} + \frac{{\left( {2 - D} \right)^{2} DR_{{CE}} }}{{\left( {1 - D} \right)^{4} R_{O} }} + f_{s} C_{O} R_{O} \hfill \\ \end{gathered} \right]$$
(27)

The non-ideal voltage gain of the fault-tolerant converter is computed as

$$\user2{\eta } = \frac{1}{{1 + {{\user2{P}_{{\user2{LS}}} } \mathord{\left/ {\vphantom {{\user2{P}_{{\user2{LS}}} } {\user2{P}_{\user2{O}} }}} \right. \kern-\nulldelimiterspace} {\user2{P}_{\user2{O}} }}}}$$
(28)
$${{\varvec{G}}}_{{\varvec{V}}-{\varvec{n}}{\varvec{o}}{\varvec{n}}-{\varvec{i}}{\varvec{d}}{\varvec{e}}{\varvec{a}}{\varvec{l}}}=\frac{{\varvec{\eta}}}{{(1-{\varvec{D}})}^{2}}$$
(29)

where GV-non-ideal represents the voltage gain of the proposed converter at non-deal condition.

$$G_{{V - non - ideal}} = \frac{1}{{(1 - D)^{2} \left[ {1 + \left[ \begin{gathered} \frac{{R_{{L1}} }}{{(1 - D)^{4} R_{O} }} + \frac{{R_{{L2}} }}{{(1 - D)^{2} R_{O} }} + \frac{{R_{C} D}}{{(1 - D)^{3} R_{O} }} + \frac{{R_{{CO}} D}}{{(1 - D)R_{O} }} + \hfill \\ \frac{{V_{F} (1 + \left( {1 - D} \right)^{2} )}}{{(1 - D)^{2} V_{O} }} + \frac{{R_{F} (1 + \left( {1 - D} \right)^{3} )}}{{(1 - D)^{4} R_{O} }} + \frac{{(2 - D)^{2} DR_{{CE}} }}{{(1 - D)^{4} R_{O} }} + f_{s} C_{O} R_{O} \hfill \\ \end{gathered} \right]} \right]}}$$
(30)

Sensitivity analysis

To study the variation of voltage gain with the duty cycle, sensitivity analysis is performed. The change in voltage gain for the various values of internal resistance of the inductor is studied by assuming both the inductors have the same internal resistance. The expression (30) is simplified by considering only the parasitic resistance of the inductor.

$${{\varvec{G}}}_{{\varvec{V}}-{\varvec{n}}{\varvec{o}}{\varvec{n}}-{\varvec{i}}{\varvec{d}}{\varvec{e}}{\varvec{a}}{\varvec{l}}}=\frac{1}{{(1-{\varvec{D}})}^{2}\left[1+\left[\frac{{{\varvec{R}}}_{{\varvec{L}}1}}{{(1-{\varvec{D}})}^{4}{{\varvec{R}}}_{{\varvec{O}}}}+\frac{{{\varvec{R}}}_{{\varvec{L}}2}}{{(1-{\varvec{D}})}^{2}{{\varvec{R}}}_{{\varvec{O}}}}\right]\right]}$$
(31)

The non-ideal voltage gain is differentiated with respect to duty cycle, D.

$$\frac{{\varvec{d}}{{\varvec{G}}}_{{\varvec{V}}{\varvec{n}}{\varvec{o}}{\varvec{n}}{\varvec{i}}{\varvec{d}}{\varvec{e}}{\varvec{a}}{\varvec{l}}}}{{\varvec{d}}{\varvec{D}}}=\frac{6{(1-{\varvec{D}})}^{5}{{\varvec{R}}}_{{\varvec{O}}}+2{{\varvec{R}}}_{{\varvec{L}}}\left(1-{\varvec{D}}\right)+{\left(1-{\varvec{D}}\right)}^{3}(2{{\varvec{R}}}_{{\varvec{L}}}+{{\varvec{R}}}_{{\varvec{O}}})}{{\left[{(1-{\varvec{D}})}^{4}{{\varvec{R}}}_{{\varvec{O}}}+{{\varvec{R}}}_{{\varvec{L}}}(1+{(1-{\varvec{D}})}^{2}\right]}^{2}}$$
(32)

Figure 4h presents the change in non-ideal voltage gain for various values of parasitic resistance of the inductor and duty cycle. From this figure, it is observed that the change in voltage gain is prominent for a higher value of the duty cycle.

Reliability evaluation

In this section, reliability analysis of the proposed topology is computed by concentrating on the failure rate analysis of input and output capacitor. The failure rate of fixed, aluminum, and electrolytic capacitors is

$$\lambda_{P} = \lambda_{b} \pi_{CV} \pi_{Q} \pi_{E}$$
(33)

The base failure rate, λb is determined by

$$\lambda_{b} = 0.00254\left[ {\left( {\frac{s}{0.5}} \right)^{3} + 1} \right]\exp \left[ {5.09\left( {\frac{T + 273}{{358}}} \right)^{5} } \right]$$
(34)

where T is the ambient temperature in °C and s is the ratio of operating to the rated voltage of capacitor. The base failure rate usually relates to the effect of temperature and electrical stress on the components.

The stress ratio of input and output capacitor of quadratic boost converter in normal mode of operation of proposed converter is (1) and (2) respectively. Similarly, the stress ratio of input and output capacitor of reconfiguration mode of operation in proposed converter is (3) and (4) respectively. The comparison of voltage stresses of the capacitors is presented in (Fig. 5a,b). Figure 5a presents the comparison of voltage stress across the input capacitor of normal and reconfiguration mode of the proposed topology. Similarly, the comparative study of voltage stress across the output capacitor of conventional quadratic boost and reconfiguration mode is presented in (Fig. 5b). Using the expression (8), the base failure rate, λb is determined for various temperatures and duty cycles. The comparison of results is presented in (Fig. 5c,d). Figure 5c presents the base failure rate of the input capacitor for 0.2 < D < 0.8 and various temperatures. Figure 5d presents the base failure rate of the output capacitor for 0.2 < D < 0.8 and various temperatures. From this comparative study, it is noted that the reconfiguration mode of operation has a lower base failure rate in both the input capacitor, CR and the output capacitor, CoR.

Fig. 5
figure 5

Reliability assessment (a) Voltage stress across input capacitor (b) Voltage stress across output capacitor (c) Base failure rate of input capacitor (d) Base failure rate of output capacitor (e) Comparison of base failure rate of capacitors for chosen ratings (f) Comparison of failure rate of capacitors for chosen ratings (g) Failure rate analysis of switch (h) Failure rate analysis of diode (i) Failure rate analysis of inductor (j) Failure rate analysis of capacitor.

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Using expression (13), the failure rate of the capacitor is determined. In this expression, πCV is the capacitance factor, πE is the environment factor and πQ is the quality factor. πCV is obtained using the capacitance value of the capacitor. It is computed by

$$\pi_{CV} = 0.34C^{0.18}$$
(35)

where C is the value of the capacitor. Since the application considered for this study is ground mounted (GM) the environment factor, πE is chosen from the manual as 12 for GM. The quality factor, πQ is considered as 0.03 for S quality. For this analysis, 1-kW converter with Vdc = 50 V, Vo = 200 V, T = 25 °C and D = 0.5. The base failure rate and failure rate of capacitors are calculated and compared in (Fig. 5e,f). Figure 5 (e) is obtained by evaluating the base failure rate of capacitors as per the expression presented in Fig. 5j. Finally, the failure rate of the capacitor as presented in Fig. 5f is determined using the expressions depicted in (Fig. 5j). From this comparison, it is observed that the failure rate of input and output capacitors is less in the reconfiguration state compared to the conventional quadratic boost converter.

Figure 5g–j presents the failure rate analysis of the components of power converter. The expression for the failure rate, λ for each component is given in (Fig. 5g–j). The failure rate of the switch, diode, inductor, and capacitor is 36.23 FIT, 2.19 FIT, 0.0276 FIT and 0.00244 FIT. The total failure rate of the converter is 38.45 FIT. The mean time to failure is obtained by taking the reciprocal of the total failure rate.

Considering the reliability, the cost analysis of the converter is performed. The overall system cost of the power converter consists of the cost of initial installation, downtime, and power loss. The cost of the power converter system is included in the converter installation cost. According to23, the downtime cost is assumed to be $2/hour by considering the financial loss. The downtime cost expression is obtained by assuming the time required for replacing the failed device is one week. However, for this topology, due to the presence of redundant devices, the downtime cost can be neglected.

The total cost of the converter is obtained as

$${\text{Cost}}_{{{\text{converter}}}} = {\text{ Cost}}_{{{\text{installation}}}} + {\text{ Cost}}_{{{\text{loss}}}}$$
(36)

Furthermore, it is assumed that the cost of the power loss is 10¢/kWh. By considering this, the total power loss cost is determined as

$${\text{Cost}}_{{\text{power loss}}} = \, 0.{1 }*{876}0*{\text{P}}_{{\text{total loss}}}$$
(37)

The cost of one switch, one diode, one inductor and one capacitor are $120, $3, $15, and $10 respectively. The installation cost of the converter without and with redundant components is $194 and $344. The total cost of the power converter will be $281 in the normal and reconfiguration mode because the number of components operating in both modes remains the same. Compared to23, the downtime cost is required for this fault-tolerant topology because, in the faulty phase, the converter is reconfigured without any interruption in the operation.

Comparative analysis

In this section, the proposed RFTQB topology is compared with the converter proposed in18. RFTQB topology addresses the failure of both the switch and capacitor whereas the converter derived in18 works for the switch failure. In the literature, it is observed that the capacitor in the power converter is more prone to failure. RFTQB topology solves the failure of both input and output capacitors along with the switch failure. In addition, the reconfigured topology proposed in18, reconfigured from buck and boost to buck-boost converter whereas RFTQB topology reconfigures to the same topology without disturbing the voltage and current gain of the topology with the failure in switch and capacitor.

The proposed RFTQB topology is compared to the FT topology proposed in18 and24 and its pictorial representation is depicted in (Fig. 6a–c). In Fig. 6a, it is noted that the derived FT topology with single-level redundancy changes the configuration of the topology. Similarly, a fault-tolerant proposed in24 is considered for comparison and its transition in configuration during switch fault is presented in Fig. 6b. In this topology, to address the switch fault, the buck-boost converter is integrated with a positive output Luo converter. As a result, a high-gain dc converter is derived with two switches. If switch S1 fails, the proposed converter is reconfigured to positive output Luo converter and for switch S2, it is reconfigured to boost converter. This topology also addresses only the switch fault.

Fig. 6
figure 6

Comparative analysis (a) Converter proposed in18 (b) Converter proposed in24 (c) RFTQB topology.

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In the case of RFTQB topology, it is noted that the reconfigured topology does not change the configuration of the topology and voltage gain of the converter at the time of fault in switch and capacitors (two-level redundancy) as depicted in Fig. 6c.

Simulation results

The RFTQB converter is simulated in MATLAB/Simulink and the results are discussed in this section. Figure 7 (ae) present the simulation results of the proposed topology. For this simulation study, Vdc = 50 V, Vo = 200 V, fs = 20 kHz and D = 0.5 are considered. From Fig. 7a, it is observed that the output voltage remains constant for both the modes of the operations. Reduction in capacitor stress in the reconfiguration mode is validated in (Fig. 7b) by showcasing the voltage across the input and output capacitor.

Fig. 7
figure 7

Simulation results (a) Output voltage (b) capacitor voltage (c) Switch voltage (d) Diode voltage (e) Input and output voltage/current.

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Maximum voltage stress across the switch in normal and reconfiguration mode remain the same which is depicted in (Fig. 7c). Finally, the diode voltages are presented in (Fig. 7d).

The efficiency of the proposed topology in both modes of operation is analysed and it is observed that the efficiency of the converter remains the same in both states. To validate this, the input and output currents of the converter are observed and presented in (Fig. 7e).

Hardware results

In rural areas of India with difficult topography, a centralized DC microgrid system is not mostly recommended. An inverterless solar rooftop system is a workable alternative that suggested in25 to power these off-grid residences in challenging terrain. In this paper, a 1-kW rooftop solar PV system suitable for individual homes located in rural areas in difficult terrain is proposed and tested. Additional components (2 capacitors and 1 switch) used in the circuit are redundant components and it comes to operation only when the main components fail. Most of the reconfigurable fault-tolerant converters in the literature12,13,18,26 are proposed with additional redundant components to avoid uninterruptible power supply.

Solar power converters must adhere to the International electrotechnical commission (IEC) 62109-1 safety standard. The minimal specifications for the design and production of power conversion equipment for the prevention of electric shock, energy, fire, mechanical, and other risks are outlined in this standard.

An experimental prototype has been built for testing and validating the fault-tolerant operation of the proposed reconfigurable quadratic boost converter. The specifications/ratings of the components of the implemented hardware are presented in Table3. A digital controller with a gate driver circuit is used to generate a pulse for the Semikron switch in the converter module. The redundancy in the capacitor and switch is tested and the results are presented in (Fig. 8a–l). A digital control scheme is included for voltage regulation with the aid of a microcontroller. Appropriate current and voltage sensors are added to regulate the output voltage for the variation in the load. The fault tolerance control is coordinated by switching from normal to reconfiguration mode and it is carried out by a simple ON/OFF switch in the main and redundant components.

Table 3 Parameters of hardware setup.
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Fig. 8
figure 8

Hardware results (a) Photograph of 1-kW proposed converter in Ilem sheet (b) Photograph of proposed converter as a finished product with protection circuit (c) Photograph of test setup with solar panel and resistive load (d) Photograph of the solar panel (e) Input/output voltage and output capacitor voltage at 0.5 duty cycle (f) Input/output voltage and output capacitor voltage at 0.4 duty cycle (g) Diode voltages (h) SW and SWR voltage (i) Voltage across capacitor Co and CoR (j) Voltage across C and CR (k) Input current for 0.5 duty cycle with output/input voltage (l) Redundant capacitors (CR and CoR) current with input and output voltage.

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The MPPT implemented in this work is of perturb and observe scheme. In this scheme, the maximum power point is achieved through the perturbation of the solar panel operating voltage. Depending on the sensor inputs, the PV power is computed to deduct the direction of tracking and the perturbation of PV operating voltage. In case, if the power increases, the voltage is further perturbed to reach the peak point. If the power decreases, this action happens in the opposite direction. The main drawback of this technique is large oscillations around the area of the maximum power point.

The switch fault is addressed by adding a redundant switch parallel to the main switch. In the case of capacitors, the redundant capacitors are added to the topology in such a way that the converter is reconfigured into a new circuit configuration without a change in the gain of the converter. Figure 8a presents the implemented hardware in the ilem sheet for testing the prototype. Figure 8b depicts the completed circuit which is placed in the metal cabinet with agerlic Cover and protection circuit. The proposed converter is tested by connecting with the solar panel whose specification is presented in Table 2. Figure 8c illustrates the photographs of the complete setup with the solar panel whose output is drawn from the rooftop to the testing laboratory and the load.

The proposed converter is tested with a DC power supply and with a solar PV module. The picture of the solar PV module is depicted in (Fig. 8d). Figure 8e presents the working of the normal mode of operation of the proposed converter i.e., conventional quadratic boost converter. With the input voltage of 50, 190 V of output voltage with 0.5 duty cycle is presented. The normal mode of operation is also tested for a 0.4-duty cycle with a 50 V input voltage. The output voltage of 130 V is depicted in (Fig. 8f) with the output capacitor voltage equal to the output voltage. The voltage across the diode in both normal and reconfiguration modes is observed to be similar, and it is depicted in (Fig. 8g).

The validation of reconfiguration for switch and capacitor fault is depicted in (Fig. 8h–j). The main switch, SW is removed, and tested the circuit with a redundant switch, SWR, and the results obtained in this case are presented in (Fig. 8h). The voltage across the redundant switch in this faulty condition equals the output voltage.

Case (i): fault in output capacitor, Co

Figure 8i presents the fault in the output capacitor; this is obtained by isolating the capacitor with a fuse. With the relay circuit, redundant capacitor, CoR are added, and results are obtained for a 50% duty cycle. From Fig. 8i, it is noted that the voltage across the redundant output capacitor, CoR is equal to the difference between the output and input voltage.

Case (ii): fault in input capacitor, C

Figure 8j offers the fault in input capacitor; this is obtained by isolating the input capacitor, C, with fuse. With relay circuit, redundant input capacitor, CR is added, and results are obtained for 50% duty cycle. From Fig. 8j, it is noted that the voltage across the redundant input capacitor, CR is equal to (3).

Finally, Fig. 8k presents the input current/inductor current of the reconfigured fault-tolerant quadratic boost converter for a 0.5-duty cycle. Based on Fig. 8a–l, the proposed converter works well in the reconfiguration mode with input and output capacitor faults. Figure 8l presents the redundant input capacitor CR and output capacitor CoR current with output voltage working in reconfiguration mode. The efficiency of the converter is tested in both normal and reconfiguration mode and the efficiency of the RFTQB topology is 88%.

Conclusion

In this article, a reconfigured fault-tolerant quadratic boost converter is proposed for DC microgrid applications, especially for remote villages with difficult terrain. The proposed configuration is obtained by modifying the conventional quadratic boost converter by bringing the inductors and diodes to the bottom rail of the topology. As a result of this modification, 2-level redundancy can be integrated into the converter by addressing the fault in the switch and capacitors. The main features of the proposed configuration are:

  • Fault tolerance applies to both switch and capacitor faults.

  • The voltage gain of the topology remains unaltered even in the reconfiguration mode.

  • The voltage stress across the capacitors in the reconfiguration mode was observed to be reduced.

The comparison between the conventional quadratic boost converter and the proposed configuration is presented with reliability evaluation. From the analysis, it is observed that the reliability of the capacitors in the proposed converter is better compared to the conventional quadratic boost converter.

Finally, an experimental setup is tested to validate the practicability of the proposed fault-tolerant converter. Considering the salient features of the proposed topology’s reconfiguration mode, the proposed RFTQB topology can be operated in reconfiguration mode in normal operating conditions. A detailed dynamic study of the topology will be considered a future study.