Table 2 Comparisons among the proposed designs.

From: Design and assessment of even parity generator and checker circuits for nanoscale communication networks using quantum dots

Designs

Area (µm2)

Cells

Latency

Cost

Percentage improvement in cell

Even parity generator

Proposed design

0.04

23

0.75

0.0225

-

Das, et al32.

0.05

54

1.75

0.153125

57.5%

Sheikhfaal, et al33.

0.11

98

2

0.44

76.5%

Mustafa and Beigh36

0.17

99

2

0.68

76.7%

Hashemi, et al35.

0.28

168

2.75

2.1175

86.3%

Santra and Roy34

0.053

60

2

0.212

61.6%

Angizi, et al41. (1)

0.2

188

2.25

1.0125

87.7%

Poorhosseini and Hejazi42

0.08

82

2

0.32

71.9%

Angizi, et al41. (2)

0.17

109

0.75

0.09562

78.9%

Singh, et al43.

0.10

87

1.75

0.175

73.5%

Even parity checker

Proposed design

0.07

31

1.75

0.2143

-

Das, et al32.

0.08

96

1.75

0.245

67.7%

Mustafa and Beigh36

0.28

145

3

2.52

78.6%

Santra and Roy34

0.13

117

2.25

1.4175

73.5%

Sheikhfaal, et al33.

0.23

179

2

0.92

82.6%

Poorhosseini and Hejazi42

0.14

111

2

0.56

72%

Agrawal, et al44.

0.38

220

1.25

0.593

85.9%

Nano communication

Proposed circuit 4-bit

0.26

152

1.75

1.39

-

Khan, et al5. 3-bit

0.17

118

1.25

0.266

-

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