Table 5 Measured dynamic parameters (\(T_A\) = 25 \(^{\circ }\)C).

From: Design and fabrication of 4 double input NAND gate chip with excellent electrical and physical performances

Parameters

\(V_{CC}\)

Typical values

Specification value

Unit

Qualified

Min.

Max.

Transmission delay time \(t_{PLH}\)

2.0 V

38.0–39.8

/

90

ns

\(\checkmark\)

4.5 V

11.8–13.3

18

6.0 V

8.7–10.8

15

Transmission delay time \(t_{PHL}\)

2.0 V

42.1–43.9

/

90

ns

\(\checkmark\)

4.5 V

12.7–13.7

18

6.0 V

9.7–10.9

15

Allowable time \(t_{THL}\)

2.0 V

14.7–15.1

/

75

ns

\(\checkmark\)

4.5 V

7.7–8.1

15

6.0 V

4.8–5.1

13

Allowable time \(t_{TLH}\)

2.0 V

14.7–15.0

2.5

12

ns

\(\checkmark\)

4.5 V

7.7–8.1

6.0 V

4.8–5.1