Design and fabrication of 4 double input NAND gate chip with excellent electrical and physical performances

Abstract

In order to improve the performances of 4 two-input NAND so that it can be better used in the aerospace application field and in harsh environments, 4 two-input NAND gate chips were designed and successfully fabricated in this paper, based on 1.2 ${\upmu }$m P-well SPDM CMOS technological processes. The N transistors were fabricated in P-well and connected to GND via $P^+$-well. The metal wires of $V_{CC}$ use $N^+$ substrate to contact $V_{CC}$, to increase its anti-locking capability. An ESD protection circuit was designed at the input terminals, prohibiting the terminal of IC chip from being damaged by ESD stress. The performance of the device is superior to that of other similar products in the world.

Introduction

CMOS 4 two-input NAND gate IC has many advantages such as low static power dissipation, high noise margin, compatible with standard LSTTL IC, and a high driving load capacity for 10 LSTTL^1,2,3,4. When all the input terminals are at a high level, the output is at a low level only. All the inputs are clamped to $V_{CC}$ and to the ground voltage for a low level by the internal diodes to avoid electrostatic discharge damage. In order to improve the anti-static performance, the ESD protection structure was designed in this paper. The protection ring was designed to reduce latch-up probability in the cutoff region. The chips were designed based on 5 V 1.2 ${\upmu }$m P-well SPDM CMOS process. The N transistors were placed in the P-well, which was connected to GND through $P^+$-well. The metal wire layout uses as much as possible $N^+$ substrate contact connected to $V_{CC}$ to further improve the anti-latch-up capability.

Since the 4 two-Input NAND Gate IC consists of four identical parts, the layout was designed symmetrically both in horizontal and vertical directions. The maps of the active region and polycrystalline silicon were drawn based on the structure and geometric dimensions of MOSFETs^{5,6,7,8,9,10,11}. In order to decrease the chip area and to make the IC layout clear and tidy, the strips of polycrystalline silicon were tidily arranged as densely as possible according to the minimum process principle. The protection rings were designed and fabricated for the terminal devices.

Results

Design technical specifications (TA = 25 $^{\circ }$C)

• Power voltage: 2 V - 6 V

  High level output voltage ($V_{OH}$):

  $\ge$ 1.9 V ($I_{OH}$ = -20 ${\upmu }$A, $V_{CC}$ = 2.0 V)

  $\ge$ 4.4 V ($I_{OH}$ = -20 ${\upmu }$A, $V_{CC}$ = 4.5 V)

  $\ge$ 3.98 V ($I_{OH}$ = -4 mA, $V_{CC}$ = 4.5 V)

  $\ge$ 5.9 V ($I_{OH}$ = -20 ${\upmu }$A, $V_{CC}$ = 6.0 V)

  $\ge$ 5.48 V ($I_{OH}$ = -5.2 mA, $V_{CC}$ = 6.0 V)

  Low level of output voltage ($V_{OL}$):

  $\le$ 0.1 V ($I_{OL}$ = 20 ${\upmu }$A, $V_{CC}$ = 2.0 V, 4.5 V or 6.0 V)

  $\le$ 0.26 V ($I_{OL}$ = 4 mA, $V_{CC}$ = 4.5 V)

  $\le$ 0.26 V ($I_{OL}$ = 5.2 mA, $V_{CC}$ = 6.0 V)

• Power current:

  $\le$ 2 ${\upmu }$A

• Transmission delay time ($t_{PLH} /t_{PHL}$):

  $\le$ 90 ns ($C_L$ = 50 $\times$ (1±10%) pF, $V_{CC}$ = 2.0 V)

  $\le$ 18 ns ($C_L$ = 50 $\times$ (1±10%) pF, $V_{CC}$ = 4.5 V)

  $\le$ 15 ns ($C_L$ = 50 $\times$ (1±10%) pF, $V_{CC}$ = 6.0 V)

• Conversion time ($t_{TLH} /t_{THL}$):

  $\le$ 75 ns ($C_L$ = 50 $\times$ (1±10%) pF, $V_{CC}$ = 2.0 V)

  $\le$ 15 ns ($C_L$ = 50 $\times$ (1±10%) pF, $V_{CC}$ = 4.5 V)

  $\le$ 13 ns ($C_L$ = 50 $\times$ (1±10%) pF, $V_{CC}$ = 6.0 V)

• Operation temperature:

  -55 $^{\circ }$C to +125 $^{\circ }$C

Circuit structure design

Four two-input NAND gates are integrated on a chip. Each NAND gate has two inputs and one output. When all of its inputs are at a high level, the output is at a low level; otherwise, it is at a high level. It can be written as a mathematical logical expression Y = $\overline{A \cdot B}$, and its logic diagram was shown in Fig. 1.

Fig. 1

Four two-input NAND gate.

Input buffer module

The input buffer module consists of 2 inverters and 2 normally-on transmission gates. Its output voltage is identical to the input voltage, and it is used to quickly transfer signals and stabilize them. The transmission gate is designed with NMOS and PMOS transistors, where the drain and source are connected together as input and output terminals, respectively, as shown in Fig. 2.

Fig. 2

Schematic diagram of input buffer module.

The transmission gate offers several advantages, including:

• No voltage threshold loss:

  Due to the complementary operation of NMOS and PMOS transistors, the transmission gate can transfer signals without threshold voltage drop.

• No substrate bias effect:

  The design avoids the body effect, ensuring stable performance.

• Efficient low-level signal transmission:

  It can efficiently transmit low-level signals with high fidelity.

• High charging current:

  The parallel structure of NMOS and PMOS provides a high charging current for fast signal transfer.

• Full-swing signal transfer:

Since one of the two devices is always conductive, the transmission gate can transfer full-swing signals.

Intermediate and output driving stages

The circuit principle diagram of the intermediate and output driving stage is shown in Fig. 3. A NAND gate is used as an intermediate stage, and the output driver is composed of two inverters and one transmission gate. The output voltage level follows the changes in the input level. One-fourth of the schematic diagram of the designed 4 two-input NAND gate is illustrated in Fig. 4.

Fig. 3

The circuit principle diagram of the intermediate and output driving stage.

Fig. 4

Schematic diagram (1/4) of designed 4 two-NAND gate.

Simulation for functions and electrical parameters

According to the technical specifications, the static and dynamical characteristics were simulated at three temperatures TA = 25 °C, TA = − 55 °C and TA = 125 °C. The simulation results can well satisfy the application requirements and design specifications.

Function simulation

As shown in Fig. 5, the simulation results indicate the designed circuit has correct NAND gate characteristics with excellent performance for three temperatures.

Fig. 5

Function simulation waveforms.

Steady state characteristic simulation

The important DC parameters including $V_{OH}$, $V_{OL}$, $I_I$ and $I_{CC}$, were simulated for different temperatures TA = 25 $^{\circ }$C, TA = -55 $^{\circ }$C and TA = 125 $^{\circ }$C. The simulated results meet the post-service standard, as listed in Table 1.

Table 1 Steady state characteristic simulation.

Dynamical characteristic simulation

The dynamical parameters such as transmission delay times ($t_{PHL}$, $t_{PLH}$) and output conversion times ($t_{THL}$, $t_{TLH}$) were simulated at the different temperatures TA = -55 $^{\circ }$C, TA = 25 $^{\circ }$C and TA = 125 $^{\circ }$C, respectively. The simulated results satisfy the application requirements, as listed in Table 2.

Table 2 Dynamical characteristic simulation.

Threshold simulation (TA = 25 $^{\circ }$C)

• Voltage transmission characteristics for 2 V

  The simulation results for $V_{CC}$ = 2.0 V are shown in Fig. 6, and the inversion voltage of 4 two-NAND gate is 949.954 mV.

• Voltage transmission characteristics for 4.5 V

  The simulation results for $V_{CC}$ = 4.5 V are shown in Fig. 7, and the inversion voltage of 4 two-NAND gate is 2.15 V.

• Voltage transmission characteristics for 6 V

  The simulation results for $V_{CC}$ = 6.0 V are shown in Fig. 8, and the inversion voltage of 4 two-NAND gate is 2.84999 V.

Fig. 6

Threshold simulation results for VCC = 2.0 V.

Fig. 7

Threshold simulation results for VCC = 4.5 V.

Fig. 8

Threshold simulation results for VCC = 6.0 V.

Layout design

The 4 two-Input NAND Gate was constructed with four identical parts, and the layout was distributed symmetrically both in horizontal and vertical directions. The active region and polysilicon were drawn as neatly and intensively as possible according to the geometric structure and minimum process sizes, to further decrease the chip area. The protection rings were designed around the terminal device.

Layout design of unit modules

• Improvements in Antistatic ability

  As shown in Fig. 9, a diode-based ESD protection structure was designed due to its advantages, including stable performance, ease of process control, and low power dissipation during the discharge period. The structure consists of diodes formed by $P^+$ regions and the N-type substrate, connecting each input and output terminal to $V_{CC}$ with a circular junction design. Additionally, a diode formed by an $N^+$ region and a P-well is added between $V_{CC}$ and GND, as illustrated in Fig. 9b.

• Design of anti-latch-up

  The latch-up effect, also called lock-in effect, is inherent in CMOS integrated circuit. Extrinsic noise voltage at the input or output terminals can activate the parasitic bipolar NPN and PNP transistors in CMOS ICs as a thyristor, generating a damaging current from $V_{CC}$ to GND. In order to diminish the latch-up effects effectively, a protection ring structure was designed in this 4 two-Input NAND Gate. To improve anti-latch-up capability, the NMOS transistors were surrounded with a $P^+$ active region as shown in Fig. 10a, PMOS with an $N^+$ active region, as shown in Fig. 10b. The overview layout of it is shown in Fig. 11.

• Reliability consideration

  In order to improve the antistatic capability, an ESD protection structure was designed for all input and output terminals. The anti-latch-up structure was designed and a protection ring surrounds MOS transistor. The NMOS transistor was surrounded with a $P^+$ protection ring, whereas the PMOS was surrounded with an $N^+$ protection ring, increasing the anti-latch-up performance. At the same time, the distances from well boundary to source and drain regions of MOS transistors, as well as the space between NMOS and PMOS transistors, were appropriately increased to further improve the anti-latch-up capability. In order to decrease the occurrence probability of pinholes, the area covered by aluminum strip should be minimized, and the length of the aluminum (Al) strip should also be as short as possible. Using a short Al strip can further reduce the area and increase the transmission speed. The wide metal strips were replaced with ones having many trough-shaped profiles. The wide metal strip with rectangular windows spaced at a certain distance can effectively prevent or eliminate the destruction of the passivation layer caused by metal heat expansion and prevent impurities from penetrating into the active regions of chips. When the current-carrying capability of aluminum strips is much higher than the practical operation current of devices, electric migration phenomena can be avoided, ensuring operation reliability.

Fig. 9

ESD-protection diode layout: (a) Diodes at input and output terminals, which consist of $P^+$ and N-substrate; (b) A diode between $V_{CC}$ and GND, which consists of $N^+$ and P-well.

Fig. 10

Structure diagram of anti-latch-up: (a) NMOS transistor surrounded with a $P^+$ active region, (b) PMOS transistor surrounded with an $N^+$ active region.

Fig. 11

Layout of designed devices (a) Profile of layout, (b) Actual layout of Chip.

Layout verification

In order to make the design conform to technological process standard, the layout design rule was checked using DRC files. To ensure the layout to be consistent with the circuit, it was comparatively checked with the circuit using LVS files, the layouts of the chip were identical with its circuit.

Protection circuit design

An ESD protection circuit was designed at the device terminals to prevent the devices from being damaged. The charges induced by static induction cannot be leaked when the gate electrode is in a floating state because of the gate insulating resistors of CMOS devices^{1,12,13,14,15}. Since the gate oxide film of CMOS devices is very thin, when the electric field induced by the static-induction charges in the gate oxide layer is higher than the breakdown field intensity of the oxide film, the gate may be permanently damaged. Usually, when the intensity of the electric field generated by the accumulated charges on the gates is higher than 10$^7$ V/cm, the thin gate oxide film may break down. For the purpose of protecting IC chip terminals from ESD stress-induced damage, an ESD protection circuit was designed at the input terminals. In designing the ESD protection device, multiple factors such as coupling, decoupling, buffering, ballasting, triggering, and shunting need to be considered. The main design objective of the ESD protection device is to ensure that the working circuit is not used as a discharging path and thus is not damaged. When ESD occurs between any two terminals, a suitable low-resistance bypass is required. This bypass can not only absorb the ESD current but also clamp the operating voltage to prevent over-voltage. The channels of the ESD protection circuit possess excellent stability and can respond rapidly when ESD occurs without interfering with the normal operation of the chips.

Protection circuit composed of diodes

The diode D1, which is connected to $V_{CC}$ consisting of $P^+$ and N substrate, and D2, which is connected to GND composed of $N^+$ and P-well, were designed with circular junctions, increasing their breakdown voltage. As shown in Fig. 12, when the voltage input from PAD is higher than the power supply voltage $V_{CC}$, D1 turns on and the input voltage is clamped to $V_{CC}$+$V_d$ (Forward Voltage Drop $V_d$); when the input voltage is lower than GND, the diode D2 turns on and the input voltage is clamped to -$V_d$. Therefore, the applied input voltage is clamped to the range of -$V_d$ to $V_{CC}$+$V_d$, which is a safe voltage for this product.

Fig. 12

Discharging protection circuit and its layout at OE and DIR terminals.

ESD protection structure between VCC and GND

The inversely biased PN junctions with enough area between power supply and GND in large-scale IC can serve as an ESD protection circuit. Whereas for the small- or medium-scale IC, it is necessary to have an inversely biased diode between power supply and GND as a discharging channel. The protection circuit consists of many parallel diodes composed of $N^+$ connected to $V_{CC}$ and P-well which is connected to GND through $P^+$ for this product, as shown in Fig. 13.

Fig. 13

Circuit diagram and Layout of ESD protection circuit between $V_{CC}$ and GND.

Fabrication processes

The 4 two-input NAND gate chip was fabricated based on 0.2 ${\upmu }$m P-well SPDM CMOS processes, with the minimum feature size being 0.2 ${\upmu }$m. To improve the radiation-resistance of the chip, the chips were rapidly treated in a thermal ammonia atmosphere at 950 °C for 30 seconds. As a result, the interface states, fixed positive charges, and dangling bonds in the $Si-SiO_2$ interface region were considerably reduced, and the bond strength was also enhanced.

Measurement results

The measured main PCM, DC and dynamic parameters of chips were listed in Tables 3, 4 and 5, respectively.

Table 3 Measured PCM.

Table 4 Measured DC parameters.

Table 5 Measured dynamic parameters ($T_A$ = 25 $^{\circ }$C).

It can be seen from table3, 4 and 5 that the practically tested PCM, DC and dynamic parameters are much superior to the corresponding specification values. It is indicated that circuits, layouts and technological process parameters were designed correctly and properly.

Conclusions

The 4 two-input NAND gate was designed and fabricated based on 5 V, 1.2 ${\upmu }$m P-well SPDM CMOS processes, using a single metal layer and N-well P-substrate CMOS with only one polycrystalline layer. The designed and fabricated device with 4 two-input NAND gate has many excellent advantages, such as low static power consumption, high input impedance, strong anti-interference capability, large load capability, and high noise tolerance. The maximum input current is only 11 ${\upmu }$A, and the maximum power supply current is 40 ${\upmu }$A. It has a strong output driving capability and can drive at least 10 LSTTL loads. The N-transistors were fabricated in P-well and connected to GND via $P^+$-well. The metal wires of $V_{CC}$ use $N^+$ substrate contact $V_{CC}$ to increase its anti-latching capability. The performances of the designed device are superior to those of other similar products in the world. The comparisons of the performance parameters of the fabricated device with optimum specifications in the world are given in Table 6.

Table 6 Comparisons with international specifications.