Table 6 Comparisons with international specifications.

From: Design and fabrication of 4 double input NAND gate chip with excellent electrical and physical performances

Parameter

Sign

Testing conditions

Testing results

International specifications

Unit

 

lower limit

upper limit

Output high level voltage

\(V_{OH}\)

\(I_{O}\) = − 20 \({\upmu }\)A

\(V_{CC}\) = 2 V

2.003918–2.006414

1.9

/

V

\(V_{CC}\) = 4.5 V

4.252656–4.511623

4.4

/

\(V_{CC}\) = 6 V

5.9993–5.9995

5.9

/

\(I_{O}\) = − 4 mA, \(V_{CC}\) = 4.5 V

4.25016–4.511623

3.98

/

\(I_{O}\) = − 5.2 mA, \(V_{CC}\) = 6 V

6.00613–6.011014

5.48

/

Output low level voltage

\(V_{OL}\)

\(I_{O}\) = 20 \({\upmu }\)A

\(V_{CC}\) = 2 V

0.002266

/

0.1

V

\(V_{CC}\) = 4.5 V

− 0.000229–0.002266

/

0.1

\(V_{CC}\) = 6 V

− 0.000229–0.002266

/

0.1

\(I_{O}\) = 4 mA, \(V_{CC}\) = 4.5 V

0.174478–0.184462

/

0.26

\(I_{O}\) = 5.2 mA, \(V_{CC}\) = 6 V

0.184462–0.194445

/

0.26

Input current

\(I_{I}\)

\(V_{CC}\) = 6 V

− 0.014953–0.022414

/

±0.1

\({\upmu }\)A

Power supply current

\(I_{CC}\)

\(V_{CC}\) = 6 V

0.00082–0.010946

/

2

\({\upmu }\)A

Transmission delay time

\(t_{PHL}\), \(t_{PLH}\)

\(t_{r}\) = 6 ns

\(t_{f}\) = 6 ns

\(C_{L}\) = 50 pF

\(V_{CC}\) = 2 V

38.0–43.9

/

90

ns

\(V_{CC}\) = 4.5 V

11.8–13.7

/

18

\(V_{CC}\) = 6 V

8.7–10.9

/

15

Conversion time

\(t_{THL}\), \(t_{TLH}\)

\(t_{r}\) = 6 ns

\(t_{f}\) = 6 ns

\(C_{L}\) = 50 pF

\(V_{CC}\) = 2V

14.7–15.1

/

75

ns

\(V_{CC}\) = 4.5 V

7.7–8.1

/

15

\(V_{CC}\) = 6 V

4.8−5.1

/

13