Fig. 14
From: Energy-efficient design of CNTFET-based quaternary arithmetic circuits
Effect of variation in temperature for proposed quaternary logic gates in terms of (a) Pavg, (b) PDP.
Fig. 14 | Scientific Reports
From: Energy-efficient design of CNTFET-based quaternary arithmetic circuits
Effect of variation in temperature for proposed quaternary logic gates in terms of (a) Pavg, (b) PDP.
