Table 1 VRRAM array simulation parameters.

F

Feature size

30 nm

t_ox

Oxide thickness

5 nm

t_WP

WP thickness

5nm^a, 0.3 nm^b,c

t_di

Dielectric thickness

6 nm

d_p/d_ox

Core/Oxygen reservoir pillar electrode diameter/thickness

(10/5) nm^a, (20/0) nm^b,c

AR

Etching aspect ratio

30

N

Stacked layers number

8

V_SET/V_RESET

SET/RESET voltage applied to the selected WP

(2/−2.4) V^a, (−1.5/0.5) V^b,c

V_R

Read voltage applied to the selected WP

0.1 V

R_WP

WP interconnect resistance

6.67Ω^a, 14.7Ω^b,5.56Ω^c

R_pillar

Pillar electrode interconnect resistance

3.44Ω^a, 1.57Ω^b,c

I_drive

Saturation current of a vertical transistor

~150 μA

–

Min. accepted access SET write

1.5 V^a, 1 V^b,c

–

Min. accepted access RESET write

1.5 V^a, 0.4 V^b,c

–

Min. accepted read margin

100 nA

d_gap/r_CF at LRS

Tunneling gap / CF radius at the LRS

(1.8 nm/-)^a, (−/2.5 nm)^b,c

d_gap/r_CF at HRS

Tunneling gap / CF radius at the HRS

(2.3 nm/-)^a), (−/0.3 nm)^b,c