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Scaled vertical-nanowire heterojunction tunnelling transistors with extreme quantum confinement

Nature Electronics volume 8, pages 157–167 (2025)Cite this article

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Abstract

The development of data-centric computing requires new energy-efficient electronics that can overcome the fundamental limitations of conventional silicon transistors. A range of novel transistor concepts have been explored, but an approach that can simultaneously offer high drive current and steep slope switching while delivering the necessary scaling in footprint is still lacking. Here, we report scaled vertical-nanowire heterojunction tunnelling transistors that are based on the broken-band GaSb/InAs system. The devices offer a drive current of 300 µA µm−1 and a sub-60 mV dec−1 switching slope at an operating voltage of 0.3 V. The approach relies on extreme quantum confinement at the tunnelling junction and is based on an interface-pinned energy band alignment at the tunnelling heterojunction under strong quantization.

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Fig. 1: Ultra-scaled vertical-nanowire device design.
Fig. 2: Electrical characteristics and benchmarking of vertical-nanowire Esaki diodes.
Fig. 3: Electrical characteristics of ultra-scaled vertical-nanowire tunnelling transistors.
Fig. 4: Scaling the diameter of vertical-nanowire devices.
Fig. 5: Benchmarking transistor technologies.

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Source data are provided with this paper. Other data that support the findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

This work was supported by Intel Corporation and MIT Donner Endowed Chair. B.M. and J.L. acknowledge support from DTRA (Award No. HDTRA1-20-2-0002) through the Interaction of Ionizing Radiation with Matter University Research Alliance. Device fabrication was carried out at MIT.nano, MTL and SEBL of MIT. We thank G. Dewey, U. E. Avci and A. V. Penumatcha at Intel Corporation for fruitful discussions. We thank M. Robinson at Intel Corporation for SIMS measurements. We thank X. Zhao, W. Lu and A. Vardi for insightful suggestions. We thank J. Zhu, Q. Xie and T. Zeng for helpful suggestions during device fabrication and measurements. We thank Z. Hu and P. Zhang for discussions on the physical properties of InAs.

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Authors and Affiliations

  1. Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, US

    Yanjie Shao & Jesús A. del Alamo

  2. Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA, US

    Yanjie Shao & Jesús A. del Alamo

  3. Université Paris-Saclay, CNRS, C2N, Palaiseau, France

    Marco Pala

  4. DPIA, University of Udine, Udine, Italy

    Marco Pala & David Esseni

  5. Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA, US

    Hao Tang, Baoming Wang & Ju Li

  6. Department of Nuclear Science and Engineering, Massachusetts Institute of Technology, Cambridge, MA, US

    Ju Li

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  1. Yanjie Shao
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Contributions

Y.S. and J.A.d.A. designed the study. Y.S. fabricated the devices and performed SEM imaging, electrical characterization and two-dimensional device simulations. M.P. and D.E. carried out the NEGF-based 3D quantum-transport simulations. H.T. and Y.S. carried out the first-principles calculations supervised by J.L. B.W. performed the FIB and TEM imaging of materials and devices supervised by J.L. Y.S. and J.A.d.A. wrote the manuscript. All authors read and revised the manuscript in its current form.

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Correspondence to Yanjie Shao, Marco Pala, Ju Li, David Esseni or Jesús A. del Alamo.

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Nature Electronics thanks Aryan Afzalian and Cezar Zota for their contribution to the peer review of this work.

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Shao, Y., Pala, M., Tang, H. et al. Scaled vertical-nanowire heterojunction tunnelling transistors with extreme quantum confinement. Nat Electron 8, 157–167 (2025). https://doi.org/10.1038/s41928-024-01279-w

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