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A dual-domain compute-in-memory system for general neural network inference

Nature Electronics volume 8, pages 276–287 (2025)Cite this article

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Abstract

Analogue compute-in-memory systems can offer superior energy efficiency and parallelism than conventional digital systems. However, complex regression tasks that require precise floating-point (FP) computing remain challenging with such hardware, and previous approaches have, thus, typically focused on classification tasks requiring low data precision and a limited dynamic range. Here we describe an analogue–digital unified compute-in-memory architecture for general neural network inference. The approach is based on a low-cost dual-domain FP processor and merges analogue compute-in-memory arrays with digital cores. It exhibits a 39.2 times higher energy efficiency than common FP-32 multipliers during FP neural network inference. We use this architecture to develop a memristor-based computing system and illustrate its capabilities with a fully hardware-implemented complex regression task using YOLO. The system exhibits a 2.7 times higher mean average precision (increasing from 0.27 to 0.724, mAP-50) compared with pure analogue compute-in-memory systems.

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Fig. 1: Current ACIM challenges and proposed AnDi computing architecture.
Fig. 2: Illustration of the analogue–digital unified architecture.
Fig. 3: Computation enhancement strategies.
Fig. 4: Performance analysis through two NN demonstrations.

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Data availability

The data for the hardware demonstration, including pretrained NNs, training dataset and test dataset, are available at https://github.com/wangze22/AnDi/tree/master. Further data supporting the findings of this study can be obtained from the corresponding authors upon reasonable request.

Code availability

The code that supports the findings of this study requires specific hardware platforms for execution and is available from the corresponding authors upon reasonable request.

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Acknowledgements

We thank S. Ding, W. Shi and W. Wu for supporting the development of the AnDi hardware system and Q. Qin, J. Li and T. Guo for their valuable discussions. This work is supported in part by STI 2030 – Major Projects (Grant No. 2021ZD0201205 to H.W.), the National Natural Science Foundation of China (Grant Nos. 92064001 to B.G., 624B2083 to Z.W., 62495103 to H.W. and 62025111 to H.W.), the Shanghai Municipal Science and Technology Major Project, the XPLORER Prize, the Beijing Advanced Innovation Center for Integrated Circuits and the IoT Intelligent Microsystem Center of Tsinghua University-China Mobile Communications Group Co., Ltd Joint Institute.

Author information

Authors and Affiliations

  1. School of Integrated Circuits, Tsinghua University, Beijing, China

    Ze Wang, Ruihua Yu, Zhiping Jia, Zhifan He, Tianhao Yang, Bin Gao, Zhenqi Hao, Peng Yao, Jianshi Tang, Qi Liu, He Qian & Huaqiang Wu

  2. Department of Internet of Things Technology and Application, China Mobile Research Institute, Beijing, China

    Yang Li

  3. Department of Science and Technology Innovation, China Mobile Communications Group Co. Ltd, Beijing, China

    Zhenping Hu

  4. Beijing Elemem Technology Co. Ltd, Beijing, China

    Yunrui Liu & Jianghai Lu

Authors
  1. Ze Wang
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Contributions

Z.W. designed the AnDi architecture and its key features, including the DDFP data flow, quantization and dequantization units, as well as the hybrid mapping, dynamic scheduling, feature-enhancing and hybrid online training methods. Z.J. implemented the quantization and dequantization units. Z.W. and R.Y. designed and implemented the end-to-end ACIM tool chain. Z.W. conceived and conducted the hardware inference experiments and analysed the data. T.Y. and Z.W. trained the NNs. Z.W., R.Y. and Z.J. analysed the energy efficiency and set up the data pipeline. Z.H. and R.Y. implemented the softcore CPU. R.Y. implemented the compiler for the CIM instruction set. Q.L. designed the ACIM chip. Y. Liu and J.L. supported the software development kit for the ACIM chip. Z.W., R.Y. and B.G. wrote the manuscript. P.Y., J.T., Y. Li, Z. Hu and Z. Hao reviewed and improved the quality of the manuscript. H.W., J.T. and H.Q. supervised the project.

Corresponding authors

Correspondence to Bin Gao or Huaqiang Wu.

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Extended data

Extended Data Table 1 Details of the hardware parameters used in the performance evaluation
Full size table
Extended Data Table 2 An example of a MAC tile with AnDi architecture
Full size table
Extended Data Table 3 Comparison with prior works
Full size table
Extended Data Table 4 Details of the YOLO neural networks used in the demonstration
Full size table

Extended Data Fig. 1 Comparison of energy efficiency improvement and weight splitting between the hybrid mapper in AnDi and traditional mapper for a pure ACIM system.

a, Traditional mapper for pure ACIM system. b, Hybrid mapper for AnDi system. It is evident that both systems require weight splitting when the weight size exceeds the ACIM array's capacity. However, the hybrid mapper does not split the weights into more blocks or introduce more complex memory-tracking issues than the pure ACIM system. c, Energy efficiency comparison between the traditional mapper and the hybrid mapper under different row parallelism.

Extended Data Fig. 2 An example for the analysis of delay and pipeline in the AnDi architecture.

a, Example of a MAC tile based on the AnDi architecture, considering pipeline delay conditions. The example includes a tile with a 256 × 256 ACIM array with a delay of 50 ns, and four DMAC cores, each capable of performing 64 MAC operations in parallel per computation. This design ensures that regardless of the weight assigned to the DMAC by the hybrid mapper, the DMAC’s computation delay remains within 50 ns, matching the ACIM computation delay and avoiding pipeline disruption. b, Computational units from panel (a) are encapsulated into a MAC tile. Multiple tiles form the on-chip network. c, Each tile can be designed to operate in three different computation modes: dual core mode, where both ACIM and DMAC cores work simultaneously; ACIM only mode, where only the ACIM core is active; and DMAC only mode, where only the DMAC core is active. This design aims to save energy, such that when the hybrid mapper assigns only ACIM or DMAC computations to the current tile, the other core can be completely powered off to avoid energy consumption. d, Energy consumption trends of DMAC and ACIM units as the computational load increases. The blue dashed line represents the power consumption of the AnDi system during MAC computations. e, When different weights are assigned to the DMAC, it is possible to independently switch any of the four DMAC cores on or off to save energy while still meeting the 50 ns delay requirement. The maximum computational load that each DMAC in a tile needs to handle (represented by the largest rectangle within the green area) depends on the peak energy efficiency ratio between ACIM and DMAC, which is 10:1.

Extended Data Fig. 3 AnDi Memristor based Hardware System.

a, A photo of the AnDi computation hardware system running the adaptive self-driving car. b, Block diagram of the softcore RISC-V CPU and ACIM arrays.

Extended Data Fig. 4 Maps used for turn pass rate test for the self-driving car, and mapping locations of YOLO neural network weights onto ACIM arrays.

a, Maps used for turn pass rate test for the self-driving car. b, Mapping locations of YOLO neural network weights onto ACIM arrays.

Extended Data Fig. 5 YOLO inference results with and without the enhancing layers.

All data is computed on the AnDi hardware system.

Supplementary information

Supplementary Information

Supplementary Figs. 1–7 and discussion.

Supplementary Video 1

Video demonstration of the adaptive self-driving car tested on ten different maps.

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Wang, Z., Yu, R., Jia, Z. et al. A dual-domain compute-in-memory system for general neural network inference. Nat Electron 8, 276–287 (2025). https://doi.org/10.1038/s41928-024-01315-9

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