Abstract
Numerous practical problems—ranging from machine learning to bioinformatics—can be formulated as combinatorial optimization problems. However, the computational resources required to find an optimal solution to these problems using conventional von Neumann computers increases rapidly with problem size. Alternative solvers based on Ising machines, which directly leverage equilibrium characteristics of physical systems, offer a potential solution for such problems. Here we report a coupled-oscillator-based all-to-all-connected Ising chip that is manufactured in 65-nm complementary metal–oxide–semiconductor (CMOS) technology and operates at room temperature. The approach relies on logic-based coupling, which leads to low power consumption and a large number of all-to-all-connected spins. We show that the chip can solve representative combinatorial optimization problems in a more time- and energy-efficient manner than can optimized classical solvers in software and emerging quantum annealers. Due to its energy efficiency and all-to-all connectivity, our chip can also efficiently solve dense combinatorial optimization problems that cannot be effectively mapped or solved by quantum annealers.
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Data availability
The data are available at https://figshare.com/s/99ae6e188bedee0d8ad5. Source data are provided with this paper.
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Acknowledgements
This work was supported in part by the Defense Advanced Research Projects Agency (DARPA) Quantum-Inspired Classical Computing (QuICC) programme under Air Force Research Laboratory (AFRL) contract FA8750-22-C-1034 (W.M., T.I., H.L., C.H.K., Z.Z., R.S., A.K., S.S.S., H.C. and U.R.K.), National Science Foundation (NSF) under grants 2230963 (C.H.K., Z.Z., R.S., A.K., S.S.S., H.C. and U.R.K.) and 2142248 (C.H.K., H.C. and U.R.K.), Semiconductor Research Corporation under grant 2021-AH-3024 (W.M., A.V., M.A. and C.H.K.) and Intel’s Transformative HardWare for AI (THWAI) centre (W.M.).
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H.C. was responsible for the development of the software stack for application mapping and system-level benchmarking. W.M. was responsible for the schematic and layout design of the Ising core. Z.Z. worked on techniques for application mapping to the Ising hardware. T.I. led the integration and final sign-soff of the chip. H.L. assisted with the coupler design. A.V. and M.T. wrote the test program and performed the experiments. W.M., A.V. and C.H.K. jointly analysed the test data. M.A. assisted with the circuit simulation. R.S. and A.K. helped with software stack development. C.H.K. was the overall hardware lead and project coordinator. S.S.S. and U.R.K. led the application mapping and system-level benchmarking efforts.
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The authors declare the following competing interest: US patent no. 12,261,598 (Logic based ring oscillator coupling circuit) and US patent no 11,888,484 (Circuit having fully connected ring oscillators). C.H.K. is a co-founder and the CEO of COBI, which is developing quantum-inspired computing technologies. These interests have been reviewed and managed by the University of Minnesota in accordance with its conflict of interest policies. W.M. is a co-founder and the CTO of COBI. The other authors declare no competing interests.
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Cılasun, H., Moy, W., Zeng, Z. et al. A coupled-oscillator-based Ising chip for combinatorial optimization. Nat Electron 8, 537–546 (2025). https://doi.org/10.1038/s41928-025-01393-3
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DOI: https://doi.org/10.1038/s41928-025-01393-3
