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A fast and reconfigurable sort-in-memory system based on memristors

Nature Electronics volume 8, pages 597–609 (2025)Cite this article

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Abstract

Sorting is a fundamental task in modern computing systems. Hardware sorters are typically based on the von Neumann architecture, and their performance is limited by the data transfer bandwidth and CMOS memory. Sort-in-memory using memristors could help overcome these limitations, but current systems still rely on comparison operations so that sorting performance remains limited. Here we describe a fast and reconfigurable sort-in-memory system that uses digit reads of one-transistor–one-resistor memristor arrays. We develop digit-read tree node skipping, which supports various data quantities and data types. We extend this approach with the multi-bank, bit-slice and multi-level strategies for cross-array tree node skipping. We experimentally show that our comparison-free sort-in-memory system can improve throughput by ×7.70, energy efficiency by ×160.4 and area efficiency by ×32.46 compared with conventional sorting systems. To illustrate the potential of the approach to solve practical sorting tasks, as well as its compatibility with other compute-in-memory schemes, we apply it to Dijkstra’s shortest path search and neural network inference with in situ pruning.

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Fig. 1: Overview of sorting systems.
Fig. 2: Memristor programming and TNS.
Fig. 3: TNS and CA-TNS hardware architecture and operation flow.
Fig. 4: CA-TNS strategies.
Fig. 5: TNS experiment on shortest path search.
Fig. 6: In situ pruning for PointNet++.

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Data availability

Source data are available on Zenodo at https://doi.org/10.5281/zenodo.15295945 (ref 52). Source data are provided with this paper. Other data that support the findings of this study are available from the corresponding authors upon reasonable request.

Code availability

The core source code that implements the TNS and CA-TNS is available on Zenodo at https://doi.org/10.5281/zenodo.15295945 (ref. 52). Other codes are available from the corresponding authors upon reasonable request.

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Acknowledgements

This work was supported by the National Key R&D Program of China (Grant No. 2023YFB4502200), Guangdong Provincial Key Laboratory of In-Memory Computing Chips (Grant No. 2024B1212020002), the National Natural Science Foundation of China (Grant Nos 61925401, 61927901, 8206100486, 92164302 and 92464203), Beijing Natural Science Foundation (Grant Nos L234026 and F251035) and the 111 Project (Grant No. B18001). Y.Y. acknowledges support from the Fok Ying-Tong Education Foundation.

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Authors and Affiliations

  1. Beijing Advanced Innovation Center for Integrated Circuits, School of Integrated Circuits, Peking University, Beijing, China

    Lianfeng Yu, Teng Zhang, Xile Wang, Zelun Pan, Bowen Wang, Zhaokun Jing, Jiaxin Liu, Yuqi Li, Yihang Zhu, Bonan Yan, Yaoyu Tao & Yuchao Yang

  2. Center for Brain Inspired Intelligence, Chinese Institute for Brain Research (CIBR), Beijing, China

    Zeyu Wang, Xile Wang & Yuchao Yang

  3. Guangdong Provincial Key Laboratory of In-Memory Computing Chips, School of Electronic and Computer Engineering, Peking University, Shenzhen, China

    Ziang Xie & Yuchao Yang

  4. Center for Artificial Intelligence Chips, Institute of Artificial Intelligence, Peking University, Beijing, China

    Bonan Yan, Yaoyu Tao & Yuchao Yang

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  1. Lianfeng Yu
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Contributions

L.Y. and Y.T. designed the entire concept and experiment. T.Z. fabricated and characterized the devices. L.Y. and Y.T. were in charge of the hardware system integration, designed the experimental methodologies for each part and conducted the related data analyses. L.Y., Y.T., Z.W., X.W., Z.P., B.W., Z.J., J.L, Y.L., Z.X. and Y.Z. contributed to memristor testing, circuit design, PCB integration, hardware system verification and software simulations. L.Y. and Y.T. contributed to the interpretation of the results. L.Y., Y.T. and Y.Y. wrote the paper with input from all authors. B.Y., Y.T. and Y.Y. supervised the whole project.

Corresponding authors

Correspondence to Yaoyu Tao or Yuchao Yang.

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Nature Electronics thanks Themis Prodromakis and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Extended data

Extended Data Fig. 1 Sorting example with multi-bank CA-TNS strategy.

Sorting four 4 unsigned numbers (2, 3, 9, 14) in ascending order.

Extended Data Fig. 2 Sorting example with bit-slice CA-TNS strategy.

Sorting four 4 unsigned numbers (2, 3, 9, 14) in ascending order.

Extended Data Fig. 3 Sorting example with multi-level CA-TNS strategy.

Sorting four 4 unsigned numbers (2, 3, 9, 14) in ascending order.

Supplementary information

Supplementary Information

Supplementary Sections 1–18, Figs. 1–32 and Tables 1–9.

Supplementary Video 1

CA-TNS sorting.

Supplementary Video 2

Sorting with in situ pruning.

Source data

Source Data Fig. 2

Source data for Fig. 2.

Source Data Fig. 4

Source data for Fig. 4.

Source Data Fig. 5

Source data for Fig. 5.

Source Data Fig. 6

Source data for Fig. 6.

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Yu, L., Zhang, T., Wang, Z. et al. A fast and reconfigurable sort-in-memory system based on memristors. Nat Electron 8, 597–609 (2025). https://doi.org/10.1038/s41928-025-01405-2

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