Extended Data Fig. 4: Scaling projections.
a Approximate scaling of the count of probabilistic bits (p-bits) that can be integrated per 1 mm2 area at various node sizes. As the number of p-bits increases, their proportion of the total area approaches unity, so the area of other components can be neglected in the large number of p-bits limit. This is done for the Intel and SkyWater (SKY130) p-bit projection, in which self-reported transistor and routed gate densities are compared to synthesized designs for a random 5-connected p-bit from the factorization ASIC. The SKY130 6-20-bit factorizer plot represents the density of the manufactured design, which is low due to lack of tight density constraints applied during synthesis. The Cadence 45 nm Generic PDK (GPDK) and Arizona State Predictive PDK (ASAP) points are routed designs created using Cadence Genus and Innovus. b Projected problem size (number of bits) that can be implemented at various node sizes, considering the SkyWater and Intel reported densities for a 10 mm2 and 25 mm2 design area, respectively.
