Abstract
Probabilistic Ising machines could be used to solve computationally hard problems more efficiently than deterministic algorithms on von Neumann computers. Stochastic magnetic tunnel junctions are potential entropy sources for such Ising machines. However, scaling up stochastic magnetic tunnel junction probabilistic Ising machines requires the fine control of a small magnetic energy barrier and duplication of area-intensive digital-to-analogue converter elements across large numbers of devices. The non-spintronic components of these machines are also typically created using general-purpose processors or field-programmable gate arrays. Here we report a probabilistic computer that is based on an application-specific integrated circuit fabricated using 130-nm foundry complementary metal–oxide–semiconductor technology and uses voltage-controlled magnetic tunnel junctions as its entropy source. With the system, we implement integer factorization as a representative hard optimization problem using probabilistic Ising-machine-based invertible logic gates created with 1,143 probabilistic bits. The application-specific integrated circuit uses stochastic bit sequences read from an adjacent voltage-controlled magnetic tunnel junction chip. The magnetic tunnel junctions are thermally stable in the absence of a voltage and synchronously generate random bits without the use of digital-to-analogue converter elements using the voltage-controlled magnetic anisotropy effect.
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Data availability
Source data are provided with this paper. Other data that support the plots in this paper and other findings of this study are available from the corresponding author upon reasonable request.
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Acknowledgements
This work was supported by the US National Science Foundation (NSF) under award nos. 2322572 (P.K.A.), 2425538 (P.K.A.), 2311296 (P.K.A.), 2311295 (K.Y.C.) and 2400463 (P.K.A.), and by a gift from Nokia Corporation (P.K.A.). We thank Canon ANELVA Corporation for part of the work on magnetic thin-film deposition and characterization. E.R. and G.F. acknowledge financial support from the project PRIN 2020LWPKH7 funded by the Italian Ministry of Universities and Research (MUR) and the PETASPIN Association (www.petaspin.com). E.R. also acknowledges the project PON Capitale Umano (CIR_00030) funded by the MUR.
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P.K.A. initiated the project and conceived the idea with contributions from Y.S., E.R., C.D., J.A., G.F. and K.Y.C. C.D. and J.A. designed the ASIC chip, implemented the RNG board, and performed the related testing and simulations. P.K.A. designed the V-MTJ devices with contributions from Y.S. N.D.M. and J.A.K. fabricated the V-MTJ devices. C.D., J.A. and P.K.A. wrote the manuscript with contributions from other authors. All authors discussed the results, contributed to the data analysis and commented on the manuscript. C.D. and J.A. contributed equally to this work. The study was performed under the leadership of P.K.A.
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Extended data
Extended Data Fig. 1 Revised ASIC PIM experimental results.
Frequency plot for the end state of experimental factorization attempts of the 24-bit semiprime 12,441,691 on the second ASIC which utilized the modified p-bit mapping. For readability, both orderings of each factor pair are treated as a single data point, of which the correct solution pair of 3119 and 3989 appears in a plurality of trials. A CMOS-based random number generator integrated within the PIM design area was used to generate the necessary pseudo-random numbers. The temperature was kept constant at a value of 4, over the approximately 0.8 s of convergence during each trial.
Extended Data Fig. 2 Parallel design data flow block diagram.
Data flow block diagram of a probabilistic Ising machine (PIM) with parallel updates of 5 p-bit groups, corresponding to the best possible colouring of the graph. As with the serially updating version, the input equation for each probabilistic bit (p-bit) is calculated as its h value added to a J-vector scaled sum of other p-bit values. In contrast to the serially updating version, a probabilistic logic unit (PLU) exists for every collection of at most 5 p-bits, with a p-bit of each group assigned to every PLU. If a completely even distribution is impossible, then a small number of PLUs will have less than 5 p-bits assigned and consequently be inactive for the missing p-bit group’s clock cycle.
Extended Data Fig. 3 Parallel-updating p-bit results.
a Plot of the proportions of simulated factorization trials of the 20-bit semiprime 894,479 for which the correct factor pair of 883 and 1013 was found for different parallelization sizes. The bottom axis describes the count of groups of p-bits which update simultaneously. The leftmost point has a group for each updating p-bit and thus no parallelization, while the rightmost point has 5 p-bit groups, equivalent to the best colouring of the connectivity graph. The top axis describes the number of non-input p-bits within each group if they were evenly distributed, however the connectivity structure prevents a perfectly even distribution. Temperature was linearly swept between 20 and 4 with a timeout of 223 iterations. Each datapoint represents 100 trials. b The number of iterations needed to achieve a 10% probability of finding the solution in each trial of the same problem. Each datapoint represents the minimum trial timeout length when at least 20 of 200 trials found the solution pair when iterations were increased from 0 with a 5,000-iteration step size. Temperature was linearly swept between 20 and 4.
Extended Data Fig. 4 Scaling projections.
a Approximate scaling of the count of probabilistic bits (p-bits) that can be integrated per 1 mm2 area at various node sizes. As the number of p-bits increases, their proportion of the total area approaches unity, so the area of other components can be neglected in the large number of p-bits limit. This is done for the Intel and SkyWater (SKY130) p-bit projection, in which self-reported transistor and routed gate densities are compared to synthesized designs for a random 5-connected p-bit from the factorization ASIC. The SKY130 6-20-bit factorizer plot represents the density of the manufactured design, which is low due to lack of tight density constraints applied during synthesis. The Cadence 45 nm Generic PDK (GPDK) and Arizona State Predictive PDK (ASAP) points are routed designs created using Cadence Genus and Innovus. b Projected problem size (number of bits) that can be implemented at various node sizes, considering the SkyWater and Intel reported densities for a 10 mm2 and 25 mm2 design area, respectively.
Extended Data Fig. 5 Parallelization projection.
Projected relative increase in the area, update rate, and update rate to area ratio of parallelized versions of the 80-bit factorizer design compared to a synthesized serial version on an ASAP 7 nm node. Integrated V-MTJ for random number generation and an approximately equal distribution of probabilistic bits (p-bits) to each group is assumed.
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Duffee, C., Athas, J., Shao, Y. et al. An integrated-circuit-based probabilistic computer that uses voltage-controlled magnetic tunnel junctions as its entropy source. Nat Electron 8, 784–793 (2025). https://doi.org/10.1038/s41928-025-01439-6
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DOI: https://doi.org/10.1038/s41928-025-01439-6
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