Main

The development of large-area electronics systems—such as flexible displays, wearable sensors and the Internet of Things—is driving demand for new forms of integrated circuits that offer low power consumption, mechanical flexibility and scalable fabrication1,2,3. Hybrid technology that combines n-type metal oxide and p-type organic thin-film transistors (OrTs) has emerged as a promising solution due to its low thermal budget, material complementarity and compatibility with large-area substrates4,5. The architecture provides, in particular, balanced charge transport, wide noise margins and high signal gain, making it well suited for energy-efficient logic in large-area electronics platforms6,7,8.

To meet the growing complexity and functionality demands of large-area electronics systems, increasing the transistor density without sacrificing process compatibility, thermal budget or mechanical flexibility is essential9,10. Lateral scaling has traditionally been used to enhance the circuit density, but it poses challenges for large-area electronics platforms due to limitations in resolution, substrate size and fabrication cost11,12,13. Vertical integration of hybrid transistors offers a potential solution9,11,12,13,14,15. By stacking complementary transistors in the vertical dimension, it is possible to enhance circuit density, reduce interconnect lengths and lower parasitic delays, and maintain compatibility with low-temperature, scalable processes9,11,12,13,14,15. Furthermore, vertical stacking allows multiple functional layers to be integrated, leading to higher bandwidth, reduced latency and greater energy efficiency—critical metrics for next-generation applications.

Previous work has highlighted the potential of organic and hybrid complementary circuits16,17,18,19, and recent efforts have demonstrated vertically stacked hybrid inverters using various combinations of amorphous oxide and polymer semiconductors. A gain of 70 V V−1 has, for instance, been reported using a p channel made from pentacene and an n channel made from a GaZnSn-based oxide20, and gains of 67 V V−1 (ref. 21) and 61 V V−1 (ref. 22) have been achieved through two-layer vertical integration. Solution-processed devices23 have also been shown to offer gains of over 30 V V−1 (ref. 24). However, such demonstrations have so far been limited to two stacks, constrained by interfacial roughness, thermal processing conflicts and alignment challenges23,25,26.

In this Article, we report a six-stack vertically integrated hybrid platform. Through the careful engineering of interlayer smoothness, interface stability and low-temperature fabrication, we fabricate and test over 300 hybrid inverters, which exhibit a maximum gain of 94.84 V V−1 and a low power consumption of 0.47 µW. We also develop three-dimensional (3D) NAND and NOR circuits, illustrating multilayer logic operation and providing a scalable path towards high-density, energy-efficient circuits for large-area electronics.

Fabrication

The fabrication process flow for six stacks of hybrid complementary transistors (Fig. 1) is illustrated in Supplementary Fig. 1. These stacks consist of 41 layers, fabricated using a 40-step lithography process, each containing 100 devices—approximately ten times more than the maximum number found in previously reported stacked hybrid complementary transistors20,21,22,23,24,27. This section begins with a discussion on the fabrication process, associated challenges and proposed solutions, followed by an investigation of the electrical characteristics and circuit analysis.

Fig. 1: 3D schematic of oxide, organic and hybrid complementary transistors.
figure 1

a, Structure of an OxT fabricated on a silicon substrate. The device includes an Al gate electrode, a parylene C buffer and gate dielectric, an In2O3 n-channel semiconductor and Al source (S)/drain (D) electrodes. b, Structure of an OrT with a similar gate stack as in a, but using the p-type semiconductor C16IDT-BT for the channel and Ti/Au as the S/D electrodes. c, Schematic of six vertically integrated transistor stacks combining OxTs and OrTs in an alternating fashion to form a 3D hybrid complementary transistor architecture. Stacks S1, S3 and S5 are n-type OxTs, whereas stacks S2, S4 and S6 are p-type OrTs. Parylene C is used as the interlayer dielectric to maintain electrical isolation and surface planarity during sequential layer-by-layer fabrication.

Full size image

The process started with the first stack of oxide transistors (OxTs; S1-OxTs; Supplementary Fig. 1a–g). The S1-OxT fabrication began with the deposition of a 2-µm-thick parylene C buffer via chemical vapour deposition on Radio Corporation of America-cleaned Si(100) substrates (Supplementary Fig. 1b). The subsequent step involved fabricating the bottom gate electrode. Typically, gate electrodes in the reported hybrid complementary transistor architectures have a minimum thickness of 60 nm, which can result in a surface roughness of around 2 nm (refs. 28,29). Increased surface roughness can affect the interface roughness, which is critical to manage the stackability of hybrid complementary transistors. Excessive roughness can compound with each stacking layer, leading to performance degradation in transistors and integrated circuits30,31. Therefore, we used a 20-nm-thick aluminium (Al) as the bottom gate electrode (G1), deposited by sputtering at lower d.c. power of 20 W (Supplementary Fig. 2), achieving an Al electrode surface roughness of less than 1 nm—notably smaller than that deposited using higher d.c. power.

The next step was to pattern the Al gate electrode (Supplementary Fig. 1d). In particular, the electrode patterning process plays a critical role in influencing interface roughness. Common methods like shadow mask evaporation and acetone lift-off often result in high edge roughness32,33,34,35. To examine this effect, we patterned the Al gate electrode using the widely used acetone lift-off process and compared it with results obtained using inductively coupled plasma (ICP) reactive ion etching (RIE; Supplementary Fig. 3). Profilometry measurements of Al electrodes E1–E5 (Supplementary Fig. 4a–e) confirm notable horn-like protrusions at the top corners of the electrodes patterned using the acetone lift-off process. These horns, although not drastically affecting the individual device performance, could greatly compromise devices when stacking up. By switching to the ICP-RIE method for electrodes E6–E10, we managed to avoid the protrusions (Supplementary Fig. 4f–j), ensuring smoother edges and enhanced device reliability in stacked configurations. The ICP-RIE etch condition of the Al electrode are provided in Methods, which shows that the etching rate of Al is 10 nm min−1. To avoid undesired overetching, monitoring the etching on the mask and the parylene C buffer beneath the Al gate electrode is crucial. Here an AZ5214E photoresist was used as a soft mask. Using the Al etch recipe, the etch rate for both soft mask and parylene C is around <0.5 nm min−1, which is ~20 times slower than the Al etch rate. The substantial difference in etch rates confirms the highly selective Al etching over the organic counterparts (parylene C and AZ5214E photoresist), which minimized overetching.

After patterning the bottom Al gate, a 25-nm-thick parylene C dielectric was deposited as the gate dielectric (Supplementary Fig. 1e). Supplementary Fig. 1f shows the source (S1) and drain (D1) contacts, made of 20-nm-thick Al, patterned using the same ICP-RIE method as the bottom gate (G1). Following the patterning of S1 and D1 contacts, the indium oxide (In2O3) n channel was deposited using a radio-frequency (RF) sputtering technique and patterned using the lift-off process to complete the S1-OxT fabrication (Supplementary Fig. 1g). The choice of parylene C and In2O3 as the dielectric and semiconductor was made due to the lower thermal budget (room temperature), which is crucial to improve the stackability of hybrid complementary transistors. More details on the importance of thermal budget of various materials for achieving high stackability are provided in Supplementary Note 1. The top-view schematics of the OxTs with dimensions are displayed in Supplementary Fig. 5a.

Following this, a 200-nm-thick parylene C interstack buffer layer was deposited on top of S1-OxTs (Supplementary Fig. 1h), serving as an encapsulation layer for S1-OxTs and facilitating the fabrication of the second stack of organic transistors (S2-OrTs). The fabrication process for S2-OrTs is illustrated in Supplementary Fig. 1i–m, with further details provided in Supplementary Note 2. The final step in this process involves spin coating of the p-type C16IDT-BT organic semiconductor atop the patterned source and drain electrodes (Supplementary Fig. 1m). The top-view schematics of OrTs with dimensions are presented in Supplementary Fig. 5b. For OxTs, the channel length is 20 µm, channel width is 500 µm and gate length is 10 µm. For OrTs, these dimensions are 30 µm, 1,000 µm and 3,000 µm, respectively. The larger dimensions for OrTs than those for OxTs result in enhancement-mode characteristics and balance the saturation currents between OxTs and OrTs, which is crucial for high-performance complementary metal–oxide–semiconductor (CMOS)-type logic circuits.

In particular, optimized patterning of the C16IDT-BT p channel is important to ensure compatibility with the 3D integration process, as it guarantees functional isolation between the devices, facilitates effective electrical connections between the stacks and maintains the structural integrity of multilayer 3D circuits. Therefore, in this study, we developed the passivation-mediated liquid patterning (PMLP) process (Supplementary Note 3). This process’ (Supplementary Fig. 7) success critically depends on parameters such as the thickness of the SiO2 sacrificial layer and the buffered oxide etch soaking time. For optimization, we maintained the SiO2 sacrificial layer thickness at 50 nm and tested the effect of a shorter soaking time (condition 1) and a longer soaking time (condition 2). Transfer characteristics for both conditions are shown in Supplementary Fig. 8. Although condition 1 showed no performance degradation (Supplementary Fig. 8a), condition 2 resulted in drastic performance degradation for S2-OrTs, attributed to buffered oxide etch solution damage to the p channel (Supplementary Fig. 8b). Thus, the PMLP technique proved reliable with a shorter soaking time, which was then adopted for fabricating the remaining OrTs.

Subsequently, the fabrication process continued to produce S3-OxTs, S4-OrTs, S5-OxTs and S6-OrTs, by following the same conditions as those for S1-OxTs and S2-OrTs. Finally, the six stacks of hybrid complementary transistors were realized (Supplementary Fig. 1p). Detailed information on layer thickness, deposition systems and lithography steps is available in Supplementary Table 1. Cross-sectional energy-dispersive X-ray spectra of the six stacks by transmission electron microscopy are shown in Supplementary Fig. 9.

Transistor characteristics

To perform statistical analysis and evaluate the transistor characteristics, 100 devices of each stack were measured electrically, totalling 600 devices. Among the OxTs (Fig. 2), namely, S1-OxTs (Fig. 2a), S3-OxTs (Fig. 2h) and S5-OxTs (Fig. 2o), S1-OxTs demonstrated superior gate control with the lowest subthreshold swing (SS) of 0.23 ± 0.06 V dec−1 (Fig. 2b,e), compared with 0.31 ± 0.06 V dec−1 for S3-OxTs (Fig. 2i,l) and 0.31 ± 0.10 V dec−1 for S5-OxTs (Fig. 2p,s). This indicates the potential for optimization in gate dielectric quality in S3-OxTs and S5-OxTs. The threshold voltages (VTH) of all OxTs are positive, indicating that the enhancement-mode operation is important for CMOS-type operation. S5-OxTs show the highest VTH of 3.52 ± 0.92 V (Fig. 2q,t), reflecting higher voltage needs for channel current modulation, whereas S1-OxTs and S3-OxTs presented more moderate VTH values of 1.56 ± 0.71 V (Fig. 2c,f) and 3.24 ± 0.69 V (Fig. 2j,m), respectively. In terms of ON/OFF ratio, S1-OxTs outperformed with a ratio of 6.32 × 105 (Fig. 2d,g), which was higher than those observed in S3-OxTs (Fig. 2k,n) and S5-OxTs (Fig. 2r,u), indicating a superior capability in current modulation. Additionally, electron field-effect mobility in S1-OxTs was the highest at 4.16 ± 2.33 cm2 V−1 s−1 (Supplementary Table 2), suggesting more efficient electron transport compared with the other oxide stacks.

Fig. 2: Electrical characteristics of six stacks of hybrid complementary transistors. Each stack includes 100 transistors.
figure 2

a,h,o, Transfer characteristics of S1-OxTs (a), S3-OxTs (h) and S5-OxTs (o). The shaded regions in a, h and o represent the minimum-to-maximum range of drain current measured across 100 n-type In2O3 transistors in each stack. b–d, Colour heat maps for SS (b), threshold voltage (c) and ON/OFF ratio (d) corresponding to S1-OxTs. e–g, Histogram maps for SS (e), threshold voltage (f) and ON/OFF ratio (g) corresponding to S1-OxTs. i–k, Colour heat maps for SS (i), threshold voltage (j) and ON/OFF ratio (k) corresponding to S3-OxTs. l–n, Histogram maps for SS (l), threshold voltage (m) and ON/OFF ratio (n) corresponding to S3-OxTs. p–r, Colour heat maps for SS (p), threshold voltage (q) and ON/OFF ratio (r) corresponding to S5-OxTs. s–u, Histogram maps for SS (s), threshold voltage (t) and ON/OFF ratio (u) corresponding to S5-OxTs.

Full size image

For OrTs, namely, S2-OrTs (Fig. 3a), S4-OrTs (Fig. 3h) and S6-OrTs (Fig. 3o), the performance also showed notable variation. S2-OrTs had the most efficient switching behaviour, with SS of 0.20 ± 0.06 V dec−1 (Fig. 3b,e), better than S4-OrTs and S6-OrTs, which recorded SS values of 0.27 ± 0.08 V dec−1 (Fig. 3i,l) and 0.34 ± 0.08 V dec−1 (Fig. 3p,s), respectively. The threshold voltages were consistently negative across the organic stacks, suggesting enhancement-mode operation. S2-OrTs and S4-OrTs show VTH of −1.78 ± 0.73 V (Fig. 3c,f) and −1.98 ± 0.88 V (Fig. 3j,m); S6-OrTs displayed the most negative VTH of −3.16 ± 0.75 V (Figs. 3q,t), indicating diverse p-type behaviours. The ON/OFF ratios varied, with S2-OrTs exhibiting a comparatively high ratio of 5.93 × 105 (Fig. 3d,g), compared with 1.40 × 105 (Fig. 3k,n) for S4-OrTs and 0.54 × 105 (Fig. 3r,u) for S6-OrTs, reflecting differences in current handling capabilities. Moreover, the hole field-effect mobility measurements indicated notable potential for material and interface optimization, with S2-OrTs achieving the highest field-effect mobility at 3.95 ± 2.49 cm2 V−1 s−1, markedly superior to S4-OrTs and S6-OrTs, which showed mobilities of 1.95 ± 1.84 cm2 V−1 s−1 and 1.74 ± 1.75 cm2 V−1 s−1, respectively (Supplementary Table 2).

Fig. 3: Electrical characteristics of six stacks of hybrid complementary transistors.
figure 3

Each stack includes 100 transistors. a,h,o, Transfer characteristics of S2-OrTs (a), S4-OrTs (h) and S6-OrTs (o). The shaded regions in a, h and o represent the minimum-to-maximum range of drain current (ID) measured across 100 p-type C16IDT-BT transistors in each stack. b–d, Colour heat maps for SS (b), threshold voltage (c) and ON/OFF ratio (d) corresponding to S2-OrTs. e–g, Histogram maps for SS (e), threshold voltage (f) and ON/OFF ratio (g) corresponding to S2-OrTs. i–k, Colour heat maps for SS (i), threshold voltage (j) and ON/OFF ratio (k) corresponding to S4-OrTs. l–n, Histogram maps for SS (l), threshold voltage (m) and ON/OFF ratio (n) corresponding to S4-OrTs. p–r, Colour heat maps for SS (p), threshold voltage (q) and ON/OFF ratio (r) corresponding to S6-OrTs. s–u, Histogram maps for SS (s), threshold voltage (t) and ON/OFF ratio (u) corresponding to S6-OrTs.

Full size image

The as-fabricated six stacks of hybrid complementary transistors exhibit the maximum electron field-effect mobility (S5-OxTs) of 9.82 cm2 V−1 s−1 and hole field-effect mobility (S2-OrTs) of 9.81 cm2 V−1 s−1 (Supplementary Table 2). Although these values demonstrate efficient charge carrier transport, they are below the highest reported values of 13 cm2 V−1 s−1 for electrons (OxTs) and 10 cm2 V−1 s−1 for holes (OrTs)24. This performance gap suggests that potential enhancements in material quality and structural integration could be achieved through optimized process conditions. A recent study highlighted this potential, showcasing In2O3 OxT with electron field-effect mobility as high as 113 cm2 V−1 s−1, indicating important room for improvement in the fabrication techniques36.

The hybrid complementary transistors also demonstrated maximum ON/OFF ratios (Supplementary Table 2) of 54.32 × 105 (S1-OxTs) and 33.95 × 105 (S2-OrTs), not reaching the peak values of 3 × 107 for OxTs and 4 × 107 for OrTs reported in the literature21. This discrepancy underscores the need for advancements in material quality, interface engineering and the exploration of innovative dielectric materials to further enhance the device performance. Moreover, the transistors in the study showcase threshold voltages as low as 0.22 V for S1-OxTs and −0.35 V for S2-OrTs (Supplementary Table 2), comparable to the best-reported values20,21,22,23,24,27. However, the threshold voltage of devices reported in other work for high-performance In2O3 OxTs further emphasizes the potential for achieving even lower values, contributing to reduced power consumption and enhanced digital logic circuit efficiency37,38.

Furthermore, OxTs and OrTs possess relatively comparable saturation currents, ideal for complementary inverters (Supplementary Table 2). This balance is crucial for maintaining consistent performance across the complementary circuitry.

The high SS (~230 mV dec−1) observed in this study is primarily due to room-temperature processing conditions that inhibit beneficial thermal processes that reduce interface trap densities. Additional factors such as impurities in the In2O3 source material, inconsistencies during RF magnetron sputtering and the absence of post-deposition thermal treatments further contribute to this issue. To mitigate these effects, post-fabrication treatments like O2 plasma treatment followed by annealing at 200 °C were explored, which notably improved the stability and performance of the devices (Supplementary Fig. 10). A comprehensive discussion and detailed experimental results are provided in Supplementary Note 4.

To assess the transistor performance at lower voltages, the maximum gate biasing voltage was reduced to 5 V. Transfer characteristics were subsequently recorded from all six stacks of hybrid complementary transistors (Supplementary Fig. 11). To observe device-to-device variations, 20 transistors from each stack were analysed. Parameters such as SS, VTH, ON/OFF ratio and saturation current were extracted from the transfer characteristics. These values are summarized in Supplementary Table 3. The gate current characteristics of 20 OxTs were measured over a gate voltage sweep from –5 V to +5 V. As shown in Supplementary Fig. 12a, the gate leakage current remained below 10−10 A throughout the bias range. A benchmarking comparison with reported oxide thin-film transistors integrated within hybrid complementary transistor platforms (Supplementary Fig. 12b) shows that the leakage current performance is comparable to that of previous studies22,39,40,41,42,43,44,45,46.

Supplementary Fig. 13 illustrates the interface roughness of interfaces of the six stacks of hybrid complementary transistors. It provides a quantitative basis for understanding the varying electrical performances of the devices of S1–S6. In particular, S1-OxTs and S2-OrTs exhibit particularly smoother interfaces. For instance, the bottom gate layer in S1-OxTs features a remarkably low roughness of 0.55 ± 0.31 nm, compared with those of S3-OxTs and S5-OxTs. Similarly, the parylene C dielectric in S2-OrTs shows a roughness of 1.81 ± 0.75 nm, lower than the those of S4-OrTs and S6-OrTs. These lower roughness values in S1-OxTs and S2-OrTs enhance the interface quality between the gate dielectric and the semiconductor, thereby improving carrier field-effect mobility by reducing electron scattering and trap sites that can impede the transistor performance. This is evidenced in the electrical performance data, where S1-OxTs and S2-OrTs exhibit overall better characteristics (Figs. 2 and 3).

Conversely, upper stacks of transistors have higher interface roughness values. The increased roughness probably contributes to poorer electrical performance by increasing electron and hole scattering, thereby negatively impacting both field-effect mobility and SS of the transistors. Consequently, the correlation between the thoroughly measured interface roughness values and the electrical performance of each stack underscores the critical need for process optimization. Specifically, achieving smoother interfaces in the active channel and gate dielectric layers is essential for enhancing the performance and efficiency of hybrid complementary transistors. It is important to note that with few previous works of stacked hybrid complementary transistors reporting interfacial roughness, the maximum reported interfacial roughness of 3.63 nm (Supplementary Fig. 13) is still relatively small.

Scalability and reliability characteristics

To demonstrate the scalability, submicrometre In2O3 OxTs were fabricated with reduced dimensions: channel width (WC) = 1 µm, gate length (LG) = 100 nm and channel length (LC) = 500 nm (Supplementary Fig. 14). From the transfer characteristics, we calculated the transistor parameters including threshold voltage (0.8 V), field-effect mobility (7.41 cm2 V−1 s−1), SS (200 mV dec−1) and current ON/OFF ratio (~107). These values for nanoscale OxTs are consistent with those of micrometre-scale OxTs discussed in this study.

To understand the impact of a 10-V bias on the characteristics of the transistor beneath in the 3D stacked architecture, detailed investigations into the electrical isolation between stacks were conducted. The primary focus was on determining the effectiveness of parylene C as a buffer layer in minimizing electrical interference between adjacent stacks. Experimental results (Supplementary Fig. 15) revealed that thinner buffer layers (25 nm and 50 nm) allowed notable voltage shifts in the transistor characteristics, indicating insufficient decoupling. However, increasing the buffer thickness to 200 nm effectively minimized these shifts, demonstrating adequate electrical isolation for operation up to 10 V. This suggests that buffer layer thickness plays a crucial role in ensuring the operational reliability of 3D stacked transistors. Further details of these experiments are provided in Supplementary Note 5.

The negative bias stress experiment was conducted by varying the bias stress time from 0 s to 4 ks. (Supplementary Fig. 16). Although the devices undergo bias stress, we anticipate minimizing these effects on further device development (channel interface passivation, semiconductor processing optimization, injecting contact optimization and so on). Thereafter, two devices were fabricated to investigate the effectiveness of post-fabrication treatments on enhancing device stability. Device B, which underwent an O2 plasma treatment and subsequent annealing at 200 °C, showed markedly improved stability under negative bias stress conditions compared with device A, which lacked these treatments (Supplementary Fig. 10). The effect of O2 plasma treatment followed by thermal annealing at 200 °C on the SS was evaluated. Before treatment, the SS ranged from 0.23 to 0.31 V dec−1, with a standard deviation of ±0.09 V dec−1. After treatment, the SS improved substantially to a narrower range of 0.15–0.18 V dec−1, with a mean value of 0.165 V dec−1 and a standard deviation of ±0.015 V dec−1, indicating enhanced interfacial quality and reduced trap density. This finding supports the use of an annealing process at 200 °C to enhance the performance of hybrid complementary devices and circuits. Further details on the fabrication process and experimental results are provided in Supplementary Note 4.

The reliability and thermal stability of In2O3 transistors were evaluated under various temperature conditions up to 100 °C (Supplementary Fig. 17). These results confirm that although the hybrid complementary transistors operate reliably up to 50 °C, device instability becomes notable at higher temperatures, such as 75 °C and above. This limitation is attributed to the inherently low thermal budget of the fabrication process. Improving high-temperature stability is, therefore, a key area of ongoing work and will be crucial for expanding the applicability of this technology in industrial and ambient-temperature environments. Further details on the experimental procedures and observations are provided in Supplementary Note 6.

Interstack characteristics

The largely balanced mobilities and saturation currents of OxTs and OrTs of S1–S6 (Supplementary Table 2) are beneficial for CMOS-type logic circuit performance. Comprising n-MOS and p-MOS (where MOS is metal–oxide–semiconductor), the CMOS inverter logic is a fundamental building block for realizing functional and low-power circuits. In total, there could be nine combinations of hybrid inverters by interconnecting interstack OxTs (n-MOS) and OrTs (p-MOS). Six combinations were fabricated to evaluate the logic performance of hybrid complementary transistors (Supplementary Fig. 18). Each combination includes 50 hybrid inverters. The performance of the six hybrid inverter combinations highlight the interplay between material and transistor characteristics that directly influences circuit behaviour.

Combination 1 (Fig. 4a–g) achieves trip voltage (VTRIP) of 1.00 ± 0.81 V and gain of 74.75 ± 9.77 V V−1, with a peak power consumption of 32.17 ± 44.17 µW. This configuration pairs the best-performing OxTs and OrTs of S1–S6, leveraging S1-OxTs’ high electron field-effect mobility and S2-OrTs’ low SS to produce robust gain. The high standard deviation of the peak power consumption is caused by several inverters with extremely high peak power consumption of more than 100 µW (Fig. 4d,g). Similar behaviours are applicable to combinations 2–6, too. Combination 2 (Fig. 4h–n), with VTRIP of 0.98 ± 0.84 V and gain of 72.41 ± 8.90 V V−1, shows the lowest peak power consumption among the groups at 12.98 ± 14.95 µW. Although S4-OrTs have moderate individual performance metrics, their pairing with the highly efficient S1-OxTs suggests that the excellent electrical properties of S1-OxTs help reduce the overall power usage and maintain high gain. Combination 3 (Fig. 4o–u) presents the highest gain of 77.11 ± 5.89 V V−1 and low VTRIP of 0.93 ± 0.77 V, along with peak power consumption of 10.98 ± 28.10 µW. Despite S6-OrTs being weaker in device performance, combination 3 yields the highest gain. This indicates that S1-OxTs’ superior properties might be compensating for S6-OrTs, highlighting the impact of high electron field-effect mobility and optimal interface roughness on the overall circuit performance.

Fig. 4: Electrical characteristics of inverter circuits tested using six stacks of hybrid complementary transistors.
figure 4

Each combination includes 50 hybrid inverters. a,h,o, Voltage transfer characteristics of combination 1 (a), combination 2 (h) and combination 3 (o). b–d, Colour heat maps for VTRIP (b), gain (c) and peak power consumption (d) corresponding to combination 1. e–g, Histogram maps for VTRIP (e), gain (f) and peak power consumption (g) corresponding to combination 1. i–k, Colour heat maps for VTRIP (i), gain (j) and peak power consumption (k) corresponding to combination 2. l–n, Histogram maps for VTRIP (l), gain (m) and peak power consumption (n) corresponding to combination 2. p–r, Colour heat maps for VTRIP (p), gain (q) and peak power consumption (r) corresponding to combination 3. s–u, Histogram maps for VTRIP (s), gain (t) and peak power consumption (u) corresponding to combination 3.

Full size image

Combination 4 (Supplementary Fig. 19a–g) records a higher VTRIP of 2.53 ± 0.88 V, with a gain of 74.63 ± 4.94 V V−1 and power consumption of 25.71 ± 32.18 µW. The higher VTRIP is probably due to S3-OxTs’ higher threshold voltages and greater interface roughness, which necessitate higher voltages for effective switching. In addition, the low SS and field-effect mobility of S2-OrTs help sustain high gain, demonstrating compensatory effects of the organic p-MOS in hybrid complementary transistor. Combination 5 (Supplementary Fig. 19h–n) shows a VTRIP of 2.48 ± 1.09 V and gain of 76.48 ± 8.60 V V−1, with a power consumption of 19.94 ± 25.80 µW. Similar to combination 4, the high threshold voltage of S5-OxTs elevates the trip voltage but is balanced by S2-OrTs’ lower SS, ensuring the circuit remains efficient and effective. Combination 6 (Supplementary Fig. 19o–u) features a high VTRIP of 2.61 ± 1.06 V and gain of 72.17 ± 6.62 V V−1, with a low power consumption of 9.05 ± 8.98 µW. This pairing involves moderate performers with higher interface roughness, which might explain the necessity for higher operational voltages. Nevertheless, the excellent power management between these two stacks suggests efficient energy handling despite the increased VTRIP.

The noise margin, VTRIP, gain and peak power consumption values of combinations 1–6 are summarized in Supplementary Table 4. They highlight how various transistor characteristics affect the hybrid inverter performance. The analysis underscores the importance of optimizing these properties to enhance the overall hybrid complementary transistor technology. The gain and peak power consumption values for all the six inverter combinations were extracted from the circuit characteristics shown in Supplementary Figs. 20 and 21. The maximum inverter gain (Supplementary Table 4) of the hybrid complementary transistor stacks reached 94.84 V V−1 (combination 5), a figure that surpasses the best-reported gain in the literature of 78 V V−1 (ref. 22). This exceptional performance can be attributed to the optimized transistor configurations and decent material properties of the six-stack architecture. Furthermore, the hybrid complementary inverter circuit achieves an exceptionally low peak power consumption (Supplementary Table 4) of only 0.47 µW (combination 5), which stands in stark contrast to values (for example, 210 µW) typically reported in state-of-the-art devices23. Noise margins high (NMH) and low (NML) have been determined for six different inverter combinations using the six stacks of hybrid complementary transistors. The calculated noise margin values are summarized in Supplementary Table 4. The current matching analysis of hybrid complementary inverters categorizes the combinations by the balance of n-type OxTs and p-type OrTs. Specifically, combination 4 shows balanced currents and a strategic shift in VTRIP closer to half the supply voltage (VDD/2), optimizing noise margins despite variations in current matching. This adjustment underscores the importance of threshold voltage in defining inverter performance. Further details and analysis (Supplementary Table 5) are available in Supplementary Note 7. The low-voltage performance of inverters was assessed by testing 20 devices from combination 4 at a reduced VDD of 4 V. This combination was selected for its balanced current matching between n-type OxTs and p-type OrTs. The results, including voltage transfer curves, voltage gain and output current characteristics, are shown in Supplementary Fig. 22. Key metrics like noise margin, VTRIP, gain and peak power consumption were also analysed (Supplementary Table 6). Further details are provided in Supplementary Note 8.

Furthermore, NAND and NOR logic gates were fabricated by integrating transistors from four stacks. To obtain the electrical characteristics of logic gates, two Keithley 4200 systems were used (Supplementary Fig. 23), one to apply input voltages and the other to measure the output voltage, both sharing a common ground. Inputs and outputs were controlled and recorded simultaneously using a custom Excel sheet, which helped synchronize the two systems and ensure accurate time-domain data capture for the NOR and NAND logic operations. Further experimental details are provided in Supplementary Note 9. Two cases of NAND gates were measured. NAND 1 comprised n-MOS from S1 and S3 and p-MOS from S2 and S4 (Fig. 5a); NAND 2 comprised n-MOS from S3 and S5 and p-MOS from S4 and S6 (Fig. 5c). The input voltages, VA and VB, were applied to the NAND gates, and the output voltage VOUT was measured. The VOUT values shown in Fig. 5b,d indicate a high logic ‘1’ for the input combinations ‘00’, ‘01’ and ‘10’, which aligns with the NAND logic truth table.

Fig. 5: Logic circuits and their corresponding electrical characteristics.
figure 5

a, Schematic of NAND 1 circuit using S4-OrT and S2-OrT (p-type) and S1-OxT and S3-OxT (n-type) transistors. b, Logic input–output behaviour of NAND 1 showing the voltage transitions of VA, VB and VOUT across four input states. c, Schematic of NAND 2 circuit using S4-OrT and S6-OrT (p-type) and S5-OxT and S3-OxT (n-type) transistors. d, Logic input–output behaviour of NAND 2 across four input states. e, Schematic of NOR 1 circuit using S2-OrT and S4-OrT (p-type) and S1-OxT and S3-OxT (n-type) transistors. f, Logic input–output behaviour of NOR 1 across four input states. g, Schematic of NOR 2 circuit using S6-OrT and S4-OrT (p-type) and S5-OxT and S3-OxT (n-type) transistors. h, Logic input–output behaviour of NOR 2 across four input states. All logic functions were validated, and the transitions (highlighted in shaded regions) correspond to standard logic levels: logic 0 as 0 V and logic 1 as ~10 V.

Full size image

For the NOR gates, two ways of integration, NOR 1 (Fig. 5e) and NOR 2 (Fig. 5g), were measured. In Fig. 5f,h, the measured VOUT shows a high logic 1 only when the input combination is 00 with a low logic ‘0’ for the other combinations, adhering to the NOR logic truth table. These results confirm that the as-fabricated highly integrated six stacks of hybrid complementary transistors can provide inverter, NAND and NOR logic integrated circuits. Supplementary Fig. 24 contrasts this work with reported stacked hybrid complementary transistors, highlighting larger numbers of stacks and layers owing to the lower thermal budget and other deliberate optimization techniques.

Conclusion

We have reported the development of a six-stack vertically integrated hybrid platform by reducing interfacial roughness and lowering thermal budgets. The six stacks include three stacks of n-type OxTs and three stacks of p-type OrTs, totalling 41 layers. Measurements from 600 transistors showed low SS values and high channel current ON/OFF ratios, as well as high and similar field-effect mobilities across the stacks. Saturation currents were also largely comparable. We also fabricated 300 hybrid inverters by integrating the OxTs and OrTs. The circuits exhibited a gain of 94.84 V V−1 and a low power consumption of 0.47 µW. In addition, we created 3D NOR and NAND logic gates. Our system offers strong electrical and logic performance under ambient conditions, but extending the thermal stability beyond 50 °C remains an important goal for future research to meet broader environmental and industrial reliability standards.

Methods

Electrode deposition process

d.c. sputtering was used to deposit gate, source and drain electrodes for both OxTs and OrTs in the six stacks of hybrid complementary transistors. For OxTs, a 20-nm-thick Al electrode was used as the gate, source and drain, with d.c. sputtering conditions of 20 W d.c. power, 20-s.c.c.m. Ar flow rate, and 5 mtorr. For OrTs, Ti/Au (10/20 nm) was used to make the ohmic source and drain contacts with the C16IDT-BT channel, with a 20-nm-thick Al gate electrode. The d.c. sputtering conditions for Ti and Au electrodes were 20-W d.c. power and 10-s.c.c.m. Ar flow rate at pressures of 5 and 15 mtorr, respectively.

Electrode patterning process

The ICP-RIE process was used to pattern the Al, Ti and Au electrodes. The etching rate for Al is 10 nm min−1, with conditions including a temperature of 10 °C and RF power of 130 W from the RF generator, RF power of 800 W from the ICP generator and Ar gas flow rate at 30 s.c.c.m. For Ti, the etching rate is 5 nm min−1, with a temperature of 20 °C, RF power of 100 W from the RF generator, RF power of 1,200 W from the ICP generator and gas flow rate ratio of Ar:SF6:CF4 at 15:10:15 s.c.c.m. Au is etched at a rate of 10 nm min−1, under a temperature of 10 °C, 150 W of RF power from the RF generator, 1,800 W of RF power from the ICP generator and Ar gas pressure of 30 s.c.c.m. During the electrode-etching process, a 2-µm-thick AZ514E photoresist was used as a soft mask.

Parylene C deposition and patterning process

Parylene C dimer, a solid granular material, was heated to 690 °C under a vacuum, vapourizing at 175 °C into a dimeric gas. This gas was then pyrolysed to cleave into its monomeric form. Then, the monomer gas was deposited as a thin transparent polymer film in the deposition chamber at room temperature. The thickness of the parylene C film was precisely controlled by varying the weight of the dimer powder. Supplementary Fig. 6 illustrates the relationship between the dimer weight and film thickness, enabling the deposition of films at thicknesses of 2 µm, 25 nm, 200 nm, 200 nm and 1.5 µm. These films served as the buffer (2 µm) on silicon substrates, gate dielectric (25 nm) for OxTs and OrTs, interstack buffer (200 nm), passivation layer 1 (200 nm) and passivation layer 2 (1.5 µm), respectively. Further details on this patterning process are provided in Supplementary Note 3.

The parylene C patterning process was performed using the ICP-RIE etching method. The etching rate of parylene C was 25 nm min−1 under a temperature of 10 °C, RF power of 50 W from the RF generator, 700 W from the ICP generator and a CHF3:O2 gas pressure ratio of 5:50 s.c.c.m. AZ5214 was used as the etching mask. In particular, the etching rate for parylene C and the AZ5214E mask was the same. For effective etching, the mask’s etching rate had to be lower than that of the target material. Thus, a 2-µm-thick AZ5214E soft mask was used for etching parylene C layers up to 200 nm thick. However, this mask thickness was inadequate for etching parylene C layers that were 1.5 µm and 2 µm thick. For these thicker layers, a 10-µm-thick AZ10XT photoresist layer was used as the mask instead.

In2O3 deposition and patterning process

In2O3 active channel layers (10 nm thick) were deposited at room temperature by RF sputtering. The sputtering condition was 100-W RF power, 20-s.c.c.m. Ar flow rate, 20-s.c.c.m. O2 flow rate and 10-mtorr pressure. The In2O3 channels were patterned using an acetone lift-off process.

C16IDT-BT processing conditions

C16IDT-BT was prepared as previously reported47, with a number-averaged molecular weight (Mn) of 65,000 g mol−1 and a polydispersity of 2.52, as measured by gel permeation chromatography in chlorobenzene at 80 °C against polystyrene standards. C16IDT-BT polymer semiconductors were dissolved in chlorobenzene at a concentration of 5 mg ml−1. The solution was stirred at 80 °C overnight. The semiconductors were then deposited by spin coating the solution at 2,000 rpm for 30 s, followed by thermal annealing at 100 °C for 5 min. All the processing steps were conducted in a nitrogen (N2)-filled glovebox. In this study, we utilized the PMLP approach to pattern the spin-coated C16IDT-BT channel. Details about PMLP are available in Supplementary Note 3. It is important to note that this approach is not limited to spin-coated organic channels but can also be scaled to other solution-processed organic semiconductors. This method is highly versatile and compatible with 3D integration processes.

Probing pad deposition process

We used Ti/Au (thickness, 10/100 nm) probing pads deposited using a d.c. sputtering system. The d.c. sputtering conditions for Ti and Au electrodes were set at 20-W d.c. power with 10-s.c.c.m. Ar flow rate, at pressures of 5 mtorr and 15 mtorr, respectively. In the study, probing pads were positioned far from the actual stacked layers; therefore, we opted for the lift-off process for patterning.

Transistor characterization

Electrical characterization was performed at room temperature in ambient air using a semiconductor parameter analyser. Transistor parameters, such as VTH, field-effect mobility (µFE) for both electrons and holes, SS and ON/OFF ratio, were calculated from the obtained transfer curves. The equations used to calculate µFE and SS are as follows:

$${\mu }_{\mathrm{FE}}=\frac{L}{W\times {C}_{{\rm{i}}}}\frac{\partial {I}_{{\rm{D}},\mathrm{lin}}}{\partial {V}_{{\rm{G}}}},$$
(1)
$${C}_{{\rm{i}}}=\frac{{C}_{\mathrm{ACC}}}{W\times L},$$
(2)
$$\mathrm{SS}=\frac{\partial {{(\log }_{10}[I}_{{\rm{D}}}])}{\partial {V}_{{\rm{G}}}}-1,$$
(3)

where L = channel length, W = channel width, Ci = dielectric capacitance (F cm−2), CACC = dielectric accumulation capacitance (F), ID,lin = drain current from the linear region and VG = gate voltage.