Extended Data Fig. 2: MVM timing diagram, test chip architecture, and test flow chart.
From: A lossless and fully parallel spintronic compute-in-memory macro for artificial intelligence chips
(a) The nvDCIM test chip architecture featuring the nvDCIM macro, integrated on-chip buffers, a clock generator, and SPI interfaces for data transfer. (b) nvDCIM chip test flow chart. (c) MVM timing diagram illustrating bit-serial processing for two examples: 4-bit unsigned weight with 4-bit signed input and 8-bit signed weight with 4-bit unsigned input.
