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A lossless and fully parallel spintronic compute-in-memory macro for artificial intelligence chips

Nature Electronics (2025)Cite this article

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Abstract

Non-volatile compute-in-memory macros can reduce data transfer between processing and memory units, providing fast and energy-efficient artificial intelligence computations. However, the non-volatile compute-in-memory architecture typically relies on analogue computing, which is limited in terms of accuracy, scalability and robustness. Here we report a 64-kb non-volatile digital compute-in-memory macro based on 40-nm spin-transfer torque magnetic random-access memory technology. Our macro features in situ multiplication and digitization at the bitcell level, precision-reconfigurable digital addition and accumulation at the macro level and a toggle-rate-aware training scheme at the algorithm level. The macro supports lossless matrix–vector multiplications with flexible input and weight precisions (4, 8, 12 and 16 bits), and can achieve a software-equivalent inference accuracy for a residual network at 8-bit precision and physics-informed neural networks at 16-bit precision. Our non-volatile compute-in-memory macro has computation latencies of 7.4–29.6 ns and energy efficiencies of 7.02–112.3 tera-operations per second per watt for fully parallel matrix–vector multiplications across precision configurations ranging from 4 to 16 bits.

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Fig. 1: Motivation and overview of the nvDCIM macro.
Fig. 2: Overview of the IBMD bitcell.
Fig. 3: System architecture of the nvDCIM macro.
Fig. 4: Toggle-rate-aware training scheme.

Data availability

The data that support the plots presented in this Article, as well as other findings derived from this study, are available from the corresponding authors upon reasonable request.

Code availability

Computer codes are available from the corresponding authors upon reasonable request.

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Acknowledgements

This work was supported by the National Key R&D Program of China (grant number 2022YFB4400200 to T.M.), the National Natural Science Foundation of China (grant numbers 62274081 to L.L. and 12327806 to Z.C.), Zhujiang Young Talent Program (grant number 2023QN10X177 to L.L.) and Shenzhen Stable Support Plan Program for Higher Education Institutions Research Program (grant number 20231121110457002 to L.L.). We acknowledge the SUSTech SME-Pixelcore Neuromorphic In-sensor Computing Joint Laboratory and the SUSTech SME-CIMCube Joint Laboratory for experimental support in this work.

Author information

Author notes

  1. These authors contributed equally: Humiao Li, Zheng Chai.

Authors and Affiliations

  1. School of Microelectronics, Southern University of Science and Technology, Shenzhen, China

    Humiao Li, Weirong Dong, Junjie He, Ruijie Peng, Shiheng Li, Zhen Kong, Zhengke Yang, Haoran Lyu, Haofeng Yu, Jiamin Li, Feichi Zhou, Yida Li & Longyang Lin

  2. State Key Laboratory for Mechanical Behavior of Materials, and School of Materials Science and Engineering, Xi’an Jiaotong University, Xi’an, China

    Zheng Chai, Xihui Yuan, Xianwang Wang, Xue Zhou & Tai Min

  3. Pazhou Laboratory (Huangpu) and Peng Cheng Laboratory, Guangzhou, China

    Zheng Chai, Zongben Xu & Tai Min

  4. Ministry of Education Key Laboratory of Intelligent Networks and Network Security, and School of Mathematics and Statistics, Xi’an Jiaotong University, Xi’an, China

    Zongben Xu

  5. National Laboratory of Solid-State Microstructures, and School of Materials Science and Intelligent Engineering, Nanjing University, Suzhou, China

    Tai Min

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Contributions

L.L. and T.M. conceived and supervised the project. H. Li, R.P. and L.L. designed the circuits for the nvDCIM macro and test chip. H. Li, W.D. and J.H. performed the training, quantization and inference of the NNs and implemented the toggle-rate-aware training algorithm. H. Li, Z.C., S.L., Z.K., X.Y., X.W., Z.Y., H. Lyu, H.Y. and X.Z. performed the experiments, including device characterization and building the chip-testing platform, and chip testing. H. Li, Z.C., J.L., F.Z., Y.L., Z.X., T.M. and L.L. analysed the data. H. Li, Z.C., T.M. and L.L. wrote the paper. All authors reviewed and approved the paper.

Corresponding authors

Correspondence to Tai Min or Longyang Lin.

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The authors declare no competing interests.

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Nature Electronics thanks Abdolah Amirany, Esteban Garzón and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Extended data

Extended Data Fig. 1 STT-MRAM device.

(a) Vertical structure of MTJ. RL: reference layer, which has a fixed magnetization. FL: free layer, whose magnetization can switch between parallel (P) and antiparallel (AP) orientations relative to the reference layer. HL: hard layer, which possesses strong perpendicular magnetic anisotropy (PMA). (b) Measured I-V curve of the MTJ’s magnetic resistive switching. The SEM image shows the MTJ’s critical diameter of 78 nm. (c) Measured R-V curve of the MTJ’s magnetic resistive switching, showing a clear resistance change between high-resistance (anti-parallel, AP) and low-resistance (parallel, P) states. The TMR ratio is approximately 170% at 0.1 V. TMR: Tunnel Magneto-Resistance, TMR = (RAP – RP) / RP * 100%. (d) Measured distribution of state switching voltages (VAP→P, VP→AP), with a mean VAP→P of 0.461 V (standard deviation σ = 0.029 V, CV = 6.3%) and a mean VP→AP of –0.299 V (σ = 0.020 V, CV = 6.7%). (e) Resistance distributions of the RP and RAP, where the mean RAP is 9199.2 Ω (σ = 480.7 Ω, CV = 5.2%) and the mean RP is 3363.7 Ω (σ = 171.8 Ω, CV = 5.1%). (f) Measured TMR distribution, with a mean of 173.5% (σ = 3.9%, CV = 2.2%). CV: Coefficient of Variation, CV = standard deviation (σ) / mean (μ) * 100%.

Extended Data Fig. 2 MVM timing diagram, test chip architecture, and test flow chart.

(a) The nvDCIM test chip architecture featuring the nvDCIM macro, integrated on-chip buffers, a clock generator, and SPI interfaces for data transfer. (b) nvDCIM chip test flow chart. (c) MVM timing diagram illustrating bit-serial processing for two examples: 4-bit unsigned weight with 4-bit signed input and 8-bit signed weight with 4-bit unsigned input.

Extended Data Fig. 3 Experimental and measurement platform for evaluating the nvDCIM chips.

(a) The experimental platform consists of an nvDCIM test chip, a PCB test board, and a National Instruments (NI) PXIe system, including the PXIe-6570 and PXIe-8881 modules, which handle chip control, intermediate data processing, and result visualization. Additionally, two source/measurement units (SMUs) are included in the platform for power measurements. (b) A flowchart illustrating the inference process conducted on the experimental platform. During the execution, the 64-kb nvDCIM macro performs parallel and lossless MVM operations across 4-, 8-, 12-, and 16-bit precisions for convolutional and fully connected layers. Input vectors and matrix data are supplied to the nvDCIM macro via the NI PXIe-6570 controlled through LabVIEW, which also retrieves the MVM results. Beyond this, the PXIe-6570 implements ReLU activations, pooling, Tanh activations, and batch normalization. The PXIe-8881 processes and displays the final inference results. The system supports a range of computational tasks, such as low computational precision tasks (for example, image classification with CNNs) and high computational precision tasks (for example, flow field reconstruction using PINNs).

Extended Data Fig. 4 Power and area breakdown.

(a) Area breakdown of the main macro components. (b) Power consumption breakdown of the nvDCIM macro components measured during the inference of the ResNet-20 model on the CIFAR-10 dataset.

Extended Data Fig. 5 Measured shmoo plot, energy efficiency, and test results across 24 nvDCIM chips.

(a) Measured shmoo plot of the nvDCIM macro showing the relationship between supply voltage (VDD) and maximum clock frequency (fCLK) while operating in 4-bit-input, 4-bit-weight, and 16-bit-output mode. (b) Measured energy efficiency of the nvDCIM macro versus VDD in 4-bit-input, 4-bit-weight, and 16-bit-output mode, when the weight sparsity is 50% and the input toggle rate ranges from 50% to 6.25%. F, Fail; P, Pass. (c) Wafer map showing 12 selected shots (highlighted in blue), with the Z-pattern sampling. (d) Photograph of the fabricated 12-inch wafer, showing the positions of the selected shots, corresponding to the Z-pattern used in (c). (e) Measured throughput (TOPS) distribution at VDD = 1.20 V, with a mean of 4.44 TOPS (standard deviation σ = 0.10 TOPS, CV = 2.3%). (f) Measured throughput (TOPS) distribution at VDD = 0.65 V, with a mean of 0.64 TOPS (σ = 0.03 TOPS, CV = 4.7%). (g) Measured energy efficiency (TOPS/W) distribution at VDD = 1.20 V, with a mean of 40.1 TOPS/W (σ = 1.97 TOPS/W, CV = 4.9%). (h) Measured energy efficiency (TOPS/W) distribution at VDD = 0.65 V, with a mean of 86.0 TOPS/W (σ = 8.82 TOPS/W, CV = 10.3%). CV: Coefficient of Variation, CV = standard deviation (σ) / mean (μ) * 100%.

Extended Data Fig. 6 PINN model quantization and performance.

Flow field reconstruction with PINN: A comparison of predictions for u (streamwise velocity), v (spanwise velocity), and p (pressure) at varying computational precision levels, with computational fluid dynamics (CFD) data benchmark32. (a) CFD benchmark data. (b) Predictions from the FP32 PINN model. (c) Predictions from the INT16 PINN model. (d) Predictions from the INT12 PINN model. (e) Predictions from the INT8 PINN model. (f) Predictions from the INT4 PINN model. (g) Relative L2 Norm (RL2): Temporal RL2 for u with different bit precisions and the overall RL2 for u. (h) Temporal RL2 for v with different bit precisions and the overall RL2 for v. (i) Temporal RL2 for u with different bit precisions and the overall RL2 for p.

Extended Data Fig. 7 Energy model construction.

In neural network workloads, convolution layers are mapped onto the nvDCIM hardware to perform efficient MVM operation, with feature maps and kernels assigned to input drivers and memory banks. Dynamic energy consumption is calculated by aggregating the energy costs of IBMD-bitcells, input drivers, and adders based on precomputed energy look-up tables. This model enables an evaluation of both model accuracy and energy consumption across convolutional and fully connected layers.

Extended Data Fig. 8 Toggle-rate-aware training results.

(a) Relationship between input toggle rate and accuracy for LeNet-5 INT4 model (dataset: MNIST). Increasing the regularization factor λ reduces the toggle rate while slightly impacting accuracy, demonstrating a tradeoff. (b) Energy efficiency improvement for LeNet-5. Reduction in toggle rate leads to notable energy efficiency gains, as illustrated by energy model estimations and chip-level measurements. (c) Relationship between input toggle rate and accuracy for ResNet-20 INT8 model (dataset: CIFAR-100). Similar to LeNet-5, increasing λ reduces the toggle rate with minimal accuracy degradation. (d) Energy efficiency improvement for ResNet-20 (dataset: CIFAR-100). Larger λ values result in more energy efficiency improvements.

Extended Data Table 1 Chip summary
Full size table
Extended Data Table 2 Comparison of nvDCIM with other nvCIM chips
Full size table

Supplementary information

Supplementary Information

Supplementary Figs. 1–4, Notes 1–5, Table 1 and References.

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Li, H., Chai, Z., Dong, W. et al. A lossless and fully parallel spintronic compute-in-memory macro for artificial intelligence chips. Nat Electron (2025). https://doi.org/10.1038/s41928-025-01479-y

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