Extended Data Fig. 5: Measured shmoo plot, energy efficiency, and test results across 24 nvDCIM chips.
From: A lossless and fully parallel spintronic compute-in-memory macro for artificial intelligence chips
(a) Measured shmoo plot of the nvDCIM macro showing the relationship between supply voltage (VDD) and maximum clock frequency (fCLK) while operating in 4-bit-input, 4-bit-weight, and 16-bit-output mode. (b) Measured energy efficiency of the nvDCIM macro versus VDD in 4-bit-input, 4-bit-weight, and 16-bit-output mode, when the weight sparsity is 50% and the input toggle rate ranges from 50% to 6.25%. F, Fail; P, Pass. (c) Wafer map showing 12 selected shots (highlighted in blue), with the Z-pattern sampling. (d) Photograph of the fabricated 12-inch wafer, showing the positions of the selected shots, corresponding to the Z-pattern used in (c). (e) Measured throughput (TOPS) distribution at VDD = 1.20 V, with a mean of 4.44 TOPS (standard deviation σ = 0.10 TOPS, CV = 2.3%). (f) Measured throughput (TOPS) distribution at VDD = 0.65 V, with a mean of 0.64 TOPS (σ = 0.03 TOPS, CV = 4.7%). (g) Measured energy efficiency (TOPS/W) distribution at VDD = 1.20 V, with a mean of 40.1 TOPS/W (σ = 1.97 TOPS/W, CV = 4.9%). (h) Measured energy efficiency (TOPS/W) distribution at VDD = 0.65 V, with a mean of 86.0 TOPS/W (σ = 8.82 TOPS/W, CV = 10.3%). CV: Coefficient of Variation, CV = standard deviation (σ) / mean (μ) * 100%.
