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A towards-foundry strategy for creating fully interconnected two-dimensional microprocessors

Abstract

Two-dimensional (2D) materials can be used to build next-generation electronics. However, large-scale chips containing hundreds of transistors based on 2D materials suffer from problems related to low yield and laboratory fabrication. Here we report a towards-foundry strategy to create large-scale circuits based on transferred 2D materials. The approach uses testing and repeated iterative optimization of six aspects: circuit design, layout design, material growth, material transfer, device fabrication and chip probing. We fabricate around 130 batches of samples for testing to improve the yield at each scale, from single transistors to circuit modules to a complete microprocessor. We create single transistors with nearly 100% yield, on/off ratios greater than 107 and inverter gains of approximately 400 on average. The statistical yields for the arithmetic logic unit, control unit and D-latch circuit modules are found to be 96.5%, 79.5% and 61.5%, respectively. The resulting 2D microprocessor exhibits excellent signal integrity and stability, as well as low-energy-consumption characteristics that are superior to those of early Intel central processing units.

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Fig. 1: Comparison of the chip manufacturing process between the towards-foundry strategy and a traditional process.
Fig. 2: Improvement of wafer-scale monolayer MoS2 growth and their characterizations.
Fig. 3: Statistical analysis of electrical characteristics of MoS2 transistors and basic inverter made by the transfer method.
Fig. 4: Fabrication and testing of different circuit modules.
Fig. 5: Analysis of different circuit modules and MoS2-based BNN for handwritten numeral recognition task.
Fig. 6: Demonstration of MoS2-based fully connected CPU and comparison of different circuits.

Data availability

The data that support the findings of this study are available from the corresponding authors upon reasonable request. Source data are provided with this paper.

Code availability

All codes used in this study are included in the article and are available from the corresponding authors upon request.

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Acknowledgements

This work was supported in part by the following: STI 2030—Major Projects under grant number 2022ZD0209200; the National Natural Science Foundation of China under grant number 62374099; the Beijing Natural Science Foundation–Xiaomi Innovation Joint Fund (L233009) and Beijing Natural Science Foundation (25JL005 and L248104); the Initiative Scientific Research Program of the School of Integrated Circuits, Tsinghua University; Tsinghua University Fuzhou Data Technology Joint Research Institute; and Sichuan Science and Technology Foundation under grant numbers 2025YFHZ0102 and 2025ZYD0158. This work was also sponsored by CIE-Tencent Robotics X Rhino-Bird Focused Research Program. This work was also in part supported by the Center of Nanofabrication, Tsinghua University.

Author information

Authors and Affiliations

Authors

Contributions

H.T. and T.-L.R. proposed the idea and the project. Y.L., Y.G., P.Z. and A.L. designed the experiment. J.L. and Z.W. completed the material growth. Y.G., P.Z., Z.L. and X.Z. performed the device fabrication and characterization. Z.P. finished the device and circuit simulation. A.L., H.D. and S.Y. provided the 2D-based process design kit and completed the corresponding simulation. F.W. and Y.H. provided suggestions to the device fabrication process. T.-L.R. and H.T. supervised the project. All authors discussed the results and commented on the paper.

Corresponding authors

Correspondence to Zegao Wang, Tian-Ling Ren or He Tian.

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The authors declare no competing interests.

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Nature Electronics thanks Mario Lanza and the other, anonymous, reviewer(s) for their contribution to the peer review of this work.

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Extended data

Extended Data Fig. 1 Optimization routine of MoS2 wafer films.

a, The coverage of MoS2 on C-sapphire. The coverage is equal to the ratio of the as-grown MoS2 film to the total sapphire area. b, The monolayer nucleation of MoS2 on C-sapphire. The Monolayer nucleation rate is equal to the ratio of the area occupied by a single layer of MoS2 to the area of the total MoS2 film. Both \({\text{C}}_{{\text{MoS}}_{2}}\) and \({\text{C}}_{{\text{Mono-MoS}}_{2}}\) were statistically obtained from approximately 600 CVD-grown MoS2 films.

Extended Data Fig. 2 Statistics of transfer curves, on-state current and threshold voltage.

Statistics of transfer curves, on-state current and threshold voltage for approximately 150 devices with a width-to-length ratio of (a) 7 μm/5 μm, (b) 14 μm/5 μm, (c) 45 μm/2 μm.

Supplementary information

Supplementary Information

Supplementary Figs. 1–12 and Notes 1–6.

Source data

Source Data Fig. 6

Provided input signals and measured output signals of the CPU.

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Guo, Y., Zhang, P., Liu, Y. et al. A towards-foundry strategy for creating fully interconnected two-dimensional microprocessors. Nat Electron 9, 159–169 (2026). https://doi.org/10.1038/s41928-026-01573-9

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