Fig. 3: Dynamic on-resistance degradation.

a Schematic illustration of trap states near the interface. b Schematic illustration of physical mechanism of the dynamic on-resistance (R_on,D), as a result of decreased electron density in the two-dimensional electron gas (2DEG) at the subsequent on-state after the off-state bias stress. c Synchronous pulse signal of gate-source voltage (V_GS) and drain-source voltage (V_DS) scheme for R_on,D measurement. d Normalized output curve measured with pulsed I-V system for the quiescent drain-source voltage (V_DSQ) range of 0 to 40 V, under the quiescent gate-source voltage (V_GSQ) of – 6 V. The inset shows only 5% degradation of the on-state current level compared to the initial state during the bias stress. e R_{on, D}/R_on ratio as a function of V_DSQ.