Introduction

Recent advances in producing ultrathin freestanding single-crystalline membranes have enabled heterogenous integration of dissimilar crystalline materials in a single electrical or photonic device, opening a path towards creation of devices with enhanced performance and functionalities1,2. The focus of recent studies was mainly on the membrane generation method and a rough demonstration of a prototype device fabricated via heterogeneous integration3,4,5. However, to advance this field to the next stage, it is pivotal to demonstrate the possibility of creating a device with state-of-the-art performance. Many aspects of heterogeneous integration of dissimilar materials are unknown, but perhaps the most important is the interface quality between the transferred single-crystalline membrane and the host heterostructure. To verify this, we have fabricated gallium nitride (GaN)-based high-electron-mobility transistors (HEMT) with a heterogeneously integrated SrTiO3 gate oxide layer and characterized its performance. We find that with careful fabrication and transfer of the gate oxide membrane, the device performance in regard to the oxide/HEMT interface show excellent quality, matching or exceeding that of conventionally deposited amorphous gate oxides as well as in-situ grown SiN oxides6,7,8.

GaN-based HEMT is one of the most promising structure for high-power and RF applications owing to its superior properties, such as high electron mobility and high breakdown field9,10,11. To further improve the performance and reliability beyond conventional GaN HEMTs with Schottky metal gate, metal-oxide-semiconductor (MOS)-HEMTs structures have been proposed to suppress gate leakage and passivated the GaN surface from ambient. In this regard, MOS-GaN HEMTs with various dielectric materials such as Al2O3 and HfO2 have been demonstrated12,13,14. In MOS-HEMT, the crystallization and interfacial quality of the gate dielectric material play a crucial role in determining the performance15.

Among various dielectric materials, complex-oxide materials have attracted considerable interest due to their diverse functional properties such as high dielectric constant (high-κ), ferroelectricity, magnetism, and superconducting properties making complex-oxides an attractive material system for developing next-generation devices16,17. However, epitaxial limitations in monolithic growth of dissimilar materials make it difficult to integrate single-crystalline complex-oxide materials with other material platforms such as GaN. The epitaxy of complex-oxides on substrates with different lattice constants and thermal expansion coefficients results in growth of polycrystalline films with inferior material properties. In other words, epitaxial limitations make it difficult to integrate complex-oxide materials onto conventional semiconductors while maintaining its excellent functional properties18.

To address this challenge, recent advances in fabricating single-crystalline freestanding complex-oxide membrane techniques have paved the way to seamlessly integrate complex-oxides with any arbitrary semiconductor platforms19,20,21. In this work, we demonstrate state-of-the-art GaN HEMTs utilizing heterogeneously integrated single-crystalline strontium titanium oxide (SrTiO3, abbreviated as STO) gate dielectric films. Epitaxial lift-off and direct stacking of freestanding membrane enables integration of crystalline complex-oxide materials on GaN HEMT platforms. STO, a representative perovskite material, exhibits ultrahigh dielectric constant (κ ~  300 at room temperature) and comparable breakdown field with conventional dielectric materials22,23. This material was recently utilized to demonstrate 2D-FETs successfully24. The fabricated devices show excellent electrical characteristics such as negligible hysteresis (ΔV), low subthreshold swing (SS) close to the Boltzmann limit, and low dynamic on-resistance. We conclude that the pristine interface between the transferred complex-oxide membrane and GaN is attributed to the superior performance of the devices.

Results

Structure of the STO/GaN HEMTs

Figure 1a–c shows a 3D schematic illustration, photograph, and optical microscope image of the fabricated STO/GaN HEMT device. Centimeter-scale freestanding STO membrane with a thickness of ~25 nm was transferred onto the AlGaN/GaN HEMT heterostructure as the gate insulator. The channel width, channel length, and gate length are 60 µm, 30 µm, and 4 µm, respectively. Figure 1d shows the energy band diagram of the fabricated device (the characterization and fabrication procedure are shown in Supplementary Figs. 1, 2, respectively). With an estimated valence band offset of ~0.5 eV and conduction band offset of ~0.1 eV, the STO gate insulator forms a type-I straddling band alignment with AlGaN25,26,27,28,29,30,31. Typically, the type-I negative band alignment of gate dielectric and AlGaN can potentially lead to injection of electrons from the gate toward the interface of the gate insulator and AlGaN due to the low energy barrier to electrons of negative band offset32. Furthermore, the injected electrons may be readily captured by trap states near the interface (interface and border traps) that originate from the poor interface quality and defects in the gate insulator. These electron trapping processes may negatively impact the performance of the HEMT device by causing reliability issues, such as decrease in current level and an increase in dynamic on-resistance as a result of decreasing electron density in the 2DEG at the subsequent on-state after the off-state bias stress33. However, a clean interface quality and high crystallinity of the gate insulator results in low trap states near the interface, which can compensate for the adverse effects of the type-I negative band alignment and enable highly reliable operation of the devices even with type-I negative band alignment.

Fig. 1: Structure of the STO/GaN HEMTs.
figure 1

a Schematic illustration, b photograph, c optical microscopy image and d energy band diagram of fabricated AlGaN/GaN high-electron-mobility transistors (HEMT) with SrTiO3 (STO) gate dielectric.

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Electrical characteristics

Figure 2 shows the electrical characterizations of the fabricated device. Figure 2a shows the bidirectional transfer characteristics (IDS-VGS) normalized with channel width for a drain voltage (VDS) of 0.1, 1 and 5 V. The inset shows a zoomed in subthreshold region of the transfer curve, showing negligible drain induced barrier lowering (DIBL) for increasing VDS. Figure 2b shows an identical curve in linear scale, confirming stable device operation with negligible hysteresis, which imply very low defects at the oxide/HEMT interface. To confirm the output characteristics, we measured the output curve (IDS-VDS) normalized to the channel width for a VGS range from −4 to 1 V, as shown in Fig. 2c. Regarding the pulse operation of digital circuit systems, a large hysteresis during the on-and off switching of the transistor critically degrades the stability and power efficiency of the circuit. Therefore, demonstrating a device with negligible hysteresis is crucial for ensuring stability and increasing power efficiency in digital circuits.

Fig. 2: Electrical characteristics.
figure 2

a Normalized bidirectional transfer curves of the device at drain-source voltage (VDS) = 0.1, 1 V, 5 V, respectively in log scale and b in linear scale. c Normalized output curves in gate-source voltage (VGS) range of – 4 to 1 V. d Normalized bidirectional transfer curves at VDS = 5 V. The inset shows hysteresis (ΔV) at IDS = 1 µA mm−1. e The subthreshold swing (SS) versus IDS curve for forward and reverse direction sweep. f Benchmark of minimum SS (SSmin) and ΔV of the SrTiO3 (STO)/GaN high electron mobility transistors (HEMT) compared to previously reported works of metal-oxide-semiconductor (MOS)-HEMTs.

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As shown in the Fig. 2d, the device exhibits the ON/OFF ratio ( ~ 2.6 × 107) at VDS = 5 V and the hysteresis (ΔV) of the device is nearly zero ( ~ 0.04 mA) at 1 µA mm−1. Since the hysteresis behavior in MOS-HEMT structures is typically caused by the trapping and detrapping mechanism due to border traps in the gate dielectric34, negligible hysteresis of the STO/GaN MOS-HEMT implies that the STO/GaN HEMT is free from border traps owing to the single-crystalline nature of the STO membrane and a clean STO/GaN interface. Furthermore, Fig. 2e shows the subthreshold swing (SS) extracted from the bidirectional transfer characteristics, showing an ideally low minimum SS (SSmin) value of approximately 62 mV dec−1 in both forward and reverse direction, which is close to the Boltzmann limit at room temperature (60 mV dec−1). By utilizing the following equation, the interface trap density (Dit) can be estimated from the SS value:

$${D}_{{{{{{\rm{it}}}}}}}=\frac{{C}_{{{{{{\rm{STO}}}}}}}}{q}\left(\frac{q\,{SS}}{{kT}\;{{{{\mathrm{ln}}}}}10}-1\right)$$
(1)

where k is Boltzmann constant, T is temperature and CSTO is the capacitance of STO23,24. The estimated Dit at room temperature is approximately 6.33 × 1011 eV−1 cm−2, which is even lower than MOS-HEMTs with conventional amorphous-based gate dielectric materials13,35. Thus, the steep SS of our device, which originates from the clean interface of the STO/GaN HEMT, indicates excellent gate controllability, and shows that it’s an advantageous structure for low power consumption applications. Consequently, owing to the pristine interface of the STO/GaN and the high crystallinity of STO, the STO/GaN HEMT exhibits outstanding characteristics in terms of hysteresis and SSmin compared to the other works, as shown in Fig. 2f36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51.

The STO/GaN HEMT shows the high off-state breakdown voltage (VBR) of 414 V as shown in Supplementary Fig. 3. The breakdown field (EBR) of device is calculated to be ~2 MV cm−1. Supplementary Fig. 4 shows the gate leakage characteristics of the STO/GaN HEMT. It should be noted that the gate leakage in forward bias is considerably affected by the band alignment and barrier height. As shown in Fig. 1d, STO gate insulator forms a type-I straddling band alignment with AlGaN, resulting in higher gate leakage in forward bias region due to the low energy barrier to electrons by negative band offset.

Dynamic on-resistance degradation

To further investigate the interface quality of our STO/GaN HEMT device, we measured the dynamic on-resistance (Ron,D) by varying the quasi-drain voltage (VDSQ,), which indicate the reliability of HEMTs under high quasi-bias stress. Figure 3a, b illustrates the trap states near the interface (interface and border traps) and the mechanism of the dynamic on-resistance effect, respectively. The Ron,D indicates the ratio of Ron before and after applying a stress voltage, VDSQ, at the off state. Due to the trapping of electrons at the interface between the GaN and gate dielectric layer (interface and border traps) during the bias stress, the current degrades after the bias stress, thereby increasing the Ron52. While applying a high VDSQ at the off state (VGS < VTH), the potential differences between the gate and drain electrode generate the electric field in the vertical direction, inducing electrons injection from the gate toward the interface of the gate insulator and AlGaN as shown in Fig. 3b (left). The injected electrons from the gate may be readily captured by trap states near the interface of the GaN and gate dielectric layer that originate from the poor interface quality and defects in the gate insulator, collapsing the current level due to the decreasing electron density in the 2DEG during the on state (VGS > VTH) as shown in Fig. 3b (right). Accordingly, this allows us to investigate the interface quality of the STO/GaN by analyzing the degradation of on-state current level and Ron,D36,53. The periodic drain voltage for high quiescent (VDSQ, VGSQ) and ON state was applied using a pulsed I-V system. The pulse width of VDSQ, VGSQ, and ON state are 3 ms and 2 ms, respectively. The VGSQ was kept at −6 V, while VDSQ was varied from 0 to 40 V, and the ON state drain voltage swept from 0 to 10 V as shown in Fig. 3c. Figure 3d exhibits the output characteristics for various VDSQ and VGSQ combinations, showing only 5 % degradation of the on-state current level compared to the initial state (VGSQ = VDSQ = 0 V) during the bias stress. As the amplitude of VDSQ increases, the electric field generated by the potential drops between the gate and drain electrodes is enhanced, leading to the increases of the electron trapping into the interface trap at the GaN/dielectric layer.

Fig. 3: Dynamic on-resistance degradation.
figure 3

a Schematic illustration of trap states near the interface. b Schematic illustration of physical mechanism of the dynamic on-resistance (Ron,D), as a result of decreased electron density in the two-dimensional electron gas (2DEG) at the subsequent on-state after the off-state bias stress. c Synchronous pulse signal of gate-source voltage (VGS) and drain-source voltage (VDS) scheme for Ron,D measurement. d Normalized output curve measured with pulsed I-V system for the quiescent drain-source voltage (VDSQ) range of 0 to 40 V, under the quiescent gate-source voltage (VGSQ) of – 6 V. The inset shows only 5% degradation of the on-state current level compared to the initial state during the bias stress. e Ron, D/Ron ratio as a function of VDSQ.

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To evaluate the influence of Ron,D as a function of the quiescent bias (VDSQ), we calculated the Ron,D by increasing the VDSQ from 0 V to 40 V with 5 V steps as shown in Fig. 3e. Owing to the high crystalline quality of STO and the clean interface of the STO/GaN, the maximum Ron,D only increases up to 7 %, which is much lower compared to conventional GaN MOS-HEMTs utilizing deposited amorphous oxides54.

TEM characterization of STO/GaN interface

Finally, to directly investigate the interface of the STO/GaN HEMT, a cross-sectional TEM measurement was conducted. Figure 4a shows the top view SEM image of the fabricated STO/GaN HEMT device and the investigated area of the TEM sample. The TEM was performed at the AlGaN/STO interface, (including a GaN capping layer) as illustrated in the left image of Fig. 4b. Figure 4b (right image) shows the TEM image of at the STO/GaN/AlGaN interface, which showed no defects, airgaps, unexpected interfacial layers or residues at the STO/GaN interface. We suspect that the dangling bonds of the transferred STO membrane may form atomic bonding with the underlying substrate (in our case, GaN HEMT heterostructure) by the thermal annealing process, which consistent with the previous works55,56,57,58,59 (the mechanism of the interface bonds formation is schematically illustrated in Supplementary Fig. 5). Moreover, the selected area electron diffraction (SAED) pattern (inset) of the STO region, verified the crystalline nature of the transferred STO membrane. We believe these results, along with the electrical analysis of the gate oxide interface, strongly support that the reliable operation and excellent performance of the fabricated STO gate oxide HEMT is a result of a pristine interface between highly crystalline STO gate oxide and GaN.

Fig. 4: TEM characterization of STO/GaN interface.
figure 4

a Plan-view scanning electron microscope (SEM) image of HEMT device, black box represents region of focused ion beam (FIB) milling for transmission electron microscope (TEM) analysis. b Cross-sectional TEM image of SrTiO3 (STO)/GaN interface. The inset shows selected area electron diffraction (SAED) pattern of the transferred STO.

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Conclusions

In summary, we heterogeneously integrated crystalline complex-oxide material on AlGaN/GaN HEMT as a gate dielectric by epitaxial layer transfer approach. Using STO with ultrahigh-κ properties as the gate oxide, we fabricated a MOS-HEMT device. The fabricated devices exhibited a negligible hysteresis (ΔV) at a drain current of 1 µA/mm, and a minimum SS value of 62 mV dec−1. We attribute these results to an extremely clean interface between the STO and GaN, free from interface and border traps. The dynamic on resistance measurements were performed for further interface quality analysis, in which our device only showed a maximum resistance increase of 7%.

Finally, we confirmed through TEM that no unwanted interfacial layer, residues, or airgaps between STO/GaN exists, and that the transferred STO maintains its crystalline nature. Our results demonstrate the potential of heterogeneous integration of complex-oxide materials with mature semiconductor technologies, substantially expanding the possibility of creating high performance electrical and photonic devices with novel functionalities.

Methods

Material preparation and device fabrication

A GaN HEMT, consisting of GaN capping layer (3 nm), Al0.26Ga0.74N barrier (25 nm), AlN interlayer (1 nm), GaN channel layer (2 μm) and GaN buffer layer (1 μm), was grown via metal-organic chemical vapor deposition (MOCVD) on a Si (111) substrate. The electron mobility and sheet carrier concentrations of the two-dimensional electron gas (2DEG) formed between the AlGaN/GaN interface were >1300 cm2 V−1 s−1 and ~1013 cm−2 at T = 300 K.

The integration of STO with AlGaN/GaN HEMT structure begins with the successive epitaxial growth of a water-soluble strontium aluminum oxide (Sr3Al2O6, abbreviated as SAO) sacrificial layer, followed by the growth of STO gate oxide on a single-crystalline STO (001) substrate by pulsed-laser deposition (PLD). It has been reported that the epitaxial growth of oxide film on the SAO template allows the transfer of single-crystalline STO membranes without fundamental thickness limitation60. The single-crystallinity of the epitaxially grown STO film on SAO/STO substrate is confirmed using X-ray diffraction (XRD) and electron backscatter diffraction (EBSD) map, as shown in Supplementary Fig. 1a–c. After deposition of a poly(methyl methacrylate) (PMMA) supporting layer on the as-grown STO/SAO/STO substrate via spin-coating, the stack was immersed in deionized (DI) water for ~24 hours to completely dissolve the SAO sacrificial layer61. The freestanding STO membrane with a thickness of ~25 nm was then transferred onto the AlGaN/GaN HEMT structure followed by removal of the supporting layer by acetone and rinsed by isopropyl alcohol (the complex-oxide membrane transfer procedure schematically illustrated in Supplementary Fig. 2).

The transferred membrane was patterned through standard photolithography and etched using a combination of ion milling and etching in diluted hydrofluoric acid (HF) solution. We believe that the HF etch removes most of the defects caused by the ion milling in the gate oxide membrane, leading to excellent characteristics. Mesa isolation was conducted by inductively coupled plasma reactive ion etching (ICP-RIE) using a mixture of BCl3/Cl2 gas. A Ti/Al/Ti/W (20/120/20/30 nm) stack was deposited for the source/drain electrode via e-beam evaporation, followed by rapid thermal annealing at 500 °C for 2 min in N2 environment. Finally, a Ni film ( ~ 500 nm) was deposited as the gate electrode via plasma sputtering (the low magnification cross-sectional image of the fabricated device is shown in Supplementary Fig. 6).

Electrical and material characterizations

The electrical properties of the fabricated devices were measured using a semiconductor parameter analyzer (Keithley−4200A-SCS) with a 4255-RPM module to apply pulsed signals. The structural and interfacial analysis was performed using a scanning electron microscope (SEM), focused ion beam (FIB), and transmission electron microscopy (TEM). SEM measurements were performed using JEOL high-resolution SEM (IT-500HR), ZEISS SEM with an EBSD detector. The cross-sectional TEM specimens of the fabricated devices were prepared using a Ga-focused ion beam milling (ZEISS crossbeam 540) technique. TEM measurements were performed using a JEOL ARM 200 F (NEOARM).